Knowledge Center
Knowledge Center

Ion Implants

Injection of critical dopants during the semiconductor manufacturing process.


Ion implanters, one of the workhorse tools in the fab, are used to inject critical dopants into a device. Ion implantation enables the development of the source/drain and other portions of the chip.

There are three main segments in the overall implanter market: high-current; medium-current; and high-energy. High-current implanters are used for source/drain development. Medium-current tools are used for well implants. High-energy implanters are used for deep well implants.

In planar devices, the first major implant step takes place in the front-end-of-the-line (FEOL). In simple terms, a device undergoes a shallow trench isolation (STI) process, which, in turn, divides the chip into two parts. One part of the device is PMOS, while the other is NMOS. Both parts are injected with separate dopants, which are referred to as well implants. Following that step, annealing is used to activate the dopants.

Using a medium-current implanter, dopants such as arsenic and phosphorous are usually injected into PMOS, while boron may be used in NMOS. Typically, medium-current implanters have a maximum energy range of about 900keV (triple-charge), with dose ranges from E11 to E14.

Another important and separate implant step takes place in the formation of the source/drain part of a device. In planar devices, there are three basic implants-halo; source/drain extension; and final source/drain. Typically, those implants are provided by high-current implanters.

The challenges for ion implantation are changing amid a shift toward finFETs and 3D NAND. In planar designs, the implanter generally injects dopants vertically into a substrate, which is a straightforward process.

For finFETs and 3D NAND, however, a tool must implant dopants at various and tough angles. The implanter, in turn, could miss the target, thereby impacting the uniformities, and yields, of a device. So for finFETs and 3D NAND, next-generation implanters must be more precise and provide better dosage control.

Like planar, finFETs also require well implants using medium-current implanters. But conventional vertical or zero-degree implants won’t do the trick for finFETs.

Meanwhile, in finFETs, chipmakers possibly could eliminate some high-current implant steps. For source-drain doping, chipmakers could use in-situ doping during the epitaxial process, as opposed to implantation. Source/drain extension doping may still be done by delicate implants to avoid damage.

In any case, the implants for the source/drain in finFETs must be delivered at precise angles. The big challenge is the so-called shadowing effect from the resists, which could impact the precision of the implants.

And at 7nm and beyond, the challenges will escalate. For example, it may be difficult for implanters to inject dopants into tiny fins without leaving behind some damage. So, the industry is exploring a range of future options, such as hybrid tools that combine the advantages of deposition and implantation. Still others have developed futuristic transistors that eliminate the need for ion implantation all together.

In one futuristic tool technology, Applied Materials, GlobalFoundries, Imec and SK Hynix recently described a new technology called Ion Assisted Deposition and Doping (IADD), which could be used for next-generation finFETs. Combining deposition and implantation techniques, IADD extracts ions from a plasma source, which are then directed onto the wafer. Then, the tool undergoes an ion assisted deposition process. The tool can provide about 6 knocked-in arsenic atoms for a 3-keV process at a 25 degree angle.

In another application, Nissin recently demonstrated a heated ion implantation technology for silicon-on-insulator finFETs. In the flow, the source-drain extension was formed at room temperature or heated using arsenic and other ions. Researchers enabled 20nm and 11nm thick SOI finFETs, which were perfectly crystallized by annealing.