Knowledge Center
Knowledge Center


Variability in the semiconductor manufacturing process


The manufacturing of a semiconductor chip requires many process steps, and with every step there can be imperfections, variability and alignment issues. Some of these may cause the complete failure of the die or even the wafer. Design techniques and analysis tools can be used to minimize the range of variability that will cause failure and thus increase yield. At each manufacturing node, the dimensions get smaller and thus a constant variability actually means greater percentage change. Consider that some dimensions can now be measured in terms of the number of atoms. A difference of 1 atom may represent a significant difference whereas at large geometries that may not have been significant.
There are several types of variability. Some of them are global and affect all transistors in a design in a similar manner. This could be mask or optics related. Temperature variations can also translate into changes across all transistors. More problematic is local variability that affect one or just a few transistors. This could be caused by crystal variations, contaminants or a number of other mechanisms.

When analyzing variability, models have to be built that define process extremes. These cover the range of possibilities that can be expected and each of these is referred to as a process corner.

As the number of process variabilities increase, the number of corners increases exponentially, assuming they are all independent from each other. This places limits on the number of corners that can actually be analyzed.