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Fault Simulation

Evaluation of a design under the presence of manufacturing defects


A fault simulator evaluates how a digital circuit will behave in the presence of manufacturing defects. It was a necessary tool for grading the goodness of a vector set when chips were tested by feeding functional patterns into them and looking to see that the chip produced known good results. Fault simulation was common in the 1980s before designs incorporated scan test logic. Scan test made fault simulation redundant by incorporating a small amount of additional logic into the chip that essentially turned a sequential test problem into a combinatorial problem. This had become necessary because test times were increasingly rapidly as chip designs became larger. Automatic Test Pattern Generation (ATPG) were also having increasing difficulty in producing a good and compact vector set to sue for manufacturing test.
The defects that were injected into the design are called faults and the most common is the “stuck at” fault model. This takes every wire in the design and forces it to be a logic ‘˜1’ or logic ‘˜0’. The fault is said to be detected if the behavior of the design with the fault can be detected as being different from the fault free design. Other faults include open fault, stuck inputs, shorts and delay faults. A potential detect was a fault where the faulty circuit provided an X on the output rather than a value which was known to be different that the fault free design.

Various simulation techniques were used including parallel simulation, concurrent simulation and a combination of the two techniques. In parallel fault simulation, 32 faults were run in parallel by packing the logic values into a computer word (32 bit machines were the most common at the time). By performing an arithmetic calculation on the word, 32 parallel simulations could be performed at a time with a considerable performance increased over doing each fault individually. In concurrent simulation, helper data structures were added to the simulation image. The advantage of this technique was that only those faults that diverged from the fault free behavior were evaluated.

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