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Instruction Set Architecture (ISA)

A set of basic operations a computer must support.
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Description

An instruction set architecture (ISA) defines the set of basic operations a computer must support. This includes the functional definition of operations and precise descriptions of how to invoke and access them. An ISA is independent from microarchitecture, which refers to the implementation of an ISA in a processor. A single ISA can have different microarchitecture implementations.

Typically, an ISA will include instructions for data handling and memory operations, arithmetic and logic operations, control flow operations, and coprocessor instructions.

An ISA also defines the maximum bit length for all instructions, as well as how an instruction is encoded. Having a definition of an ISA allows hardware and software development to be separated from each other. This allows a company to develop hardware while multiple other companies can develop software knowing it will run on that hardware.

There are two major classifications of ISA: CISC and RISC. Complex instruction set computer, or CISC, types include many specialized instructions that are of use to particular programs, but not universal. A CISC program will typically use fewer instructions but each instruction will take more cycles.

Reduced instruction set computer, or RISC, types have a smaller, optimized set of generalized, simple instructions with separate instructions for load/store (rather than load/store being part of another instruction). A RISC program will typically use a greater number of instructions but each instruction will take one clock cycle. Other characteristic features of RISC processors are simultaneous execution of parts through pipelining and a large number of registers.

The RISC concept was developed in the 1980s at Stanford University (MIPS) and University of California, Berkeley (RISC, commercialized as SPARC). The term CISC was only coined afterward and generally referred to everything not-RISC.

Very long instruction word (VLIW) architectures break instructions into basic operations that can be performed by the processor in parallel, called instruction-level parallelism (ILP). Each VLIW instruction encodes multiple operations and the method relies on the compiler to determine which operations can execute in parallel. The goal is to reduce hardware complexity, using processors that have relatively simple control logic because they do not perform any dynamic scheduling or reordering of operations.