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Fast, low-power inter-die conduits for 2.5D electrical signals.


Interposers are wide, extremely fast electrical signal conduits used between die in a 2.5D configuration. They can be made of both silicon and organic materials. While silicon interposers are proven technology, organic interposers are potentially easier to work with because the material is more resilient.

No matter which material is used, though, there are tradeoffs with interposers. They are more costly than conventional packaging approaches, even stacked die using wire bonds. The upside is that the interposers provide a much larger channel for electrical signals, reducing the amount of energy needed to drive those signals, minimizing resistance/capacitance (RC) delay, and shortening the distance between various IP blocks in a system and the memories associated with them. Current interposers incorporate through-silicon via for transmission of signals.

Conventional wisdom over the last five years has been that 2.5D IC packaging — chips arranged in a planar fashion around an interposer — would become the steppingstone to 3D. The idea was that interposers gradually would be replaced by through-silicon vias as chips are thinned out and bonded together. But there is a fair amount of debate these days about the accuracy of that prediction. It now appears that 2.5D and 3D ICs will co-exist for years to come once there is sufficient experience and economies of scale to make this approach more affordable and reliable.

Interposers are being used in 3D-IC configurations as a mechanical means to stack die while facilitating vertical interconnection schemes, but that doesn’t mean the interposer is just a substrate with vertical dimensions only. The interposer has complex structures with multiple layers, which are separate power and ground routing nets, along with TSVs (thru-silicon vias) with liners. (Source: “Electromagnetic Simulation And 3D-IC Interposers”)


Fig. 1: A CAD representation of a basic interposer model. Source: Ansys blog on Semiconductor Engineering.


Fig. 2: 2.5D-IC assembly that includes two substrates (silicon interposer + organic package). Source: Siemens EDA, from “Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design” blog on Semiconductor Engineering, Feb. 2022.


Fig. 2: Example of multi-die system. Source: Synopsys

Fig. 3: Example of multi-die system. Source: Synopsys, in Semiconductor Engineering article.