Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design


A new technical paper titled “Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects” was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti.

“A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The methodology combines coordinate-dependent anisotropic effective properties extractor with finite element analysis (FEA) engine, and computes mechanical stress globally on a package-scale, as well as locally on a feature-scale. For the purpose of mechanical failure analysis in the early stage of a package design, the warpage measurements were used for the tool’s calibration. The warpage measurements on printed circuit board (PCB), interposer and chiplet samples, during heating and subsequent cooling, were employed for calibrating the model parameters. The warpage simulation results on full package represented by PCB-interposer-chiplets stack demonstrate the overall good agreement with measurement profile. Performed study demonstrates that the developed electronic design automation (EDA) tool and methodology can be used for accurate warpage prediction in different types of IC stacks at early stage of package design.”

Find the technical paper here. Published March 2024.

Jun-Ho Choy, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, and Armen Kteyan. 2024. Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects. In Proceedings of the 2024 International Symposium on Physical Design (ISPD ’24). Association for Computing Machinery, New York, NY, USA, 85–90. https://doi.org/10.1145/3626184.3635284

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