Chiplets Need A New Workflow

By Ann Mutschler - 14 May, 2026 - Comments: 0

Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

By Siemens EDA - 28 Jan, 2026 - Comments: 0

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory ... » read more

A Quantum Leap in Architecture Design of Chiplet Cache Systems

By Baya Systems - 27 Aug, 2025 - Comments: 0

CacheStudio is a rapid architecture and design platform for chiplet based cache coherent systems. Cache hierarchies and parameters are specified in minutes with an abstract Python front end, and accurate workload driven simulations are performed at millions of instructions per second to uncover stateful performance indicators that require long runtimes. The results are presented interacti... » read more

Statistical BER Analysis For Two Types Of Communication Systems In Chiplet Integration (TSMC)

By Technical Paper Link - 01 Aug, 2025 - Comments: 0

An new technical paper titled "Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond" was published by researchers at TSMC. Abstract "In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitt... » read more

Baya Systems: Moving Data Faster

By Ed Sperling And Emma Riverso - 17 Jun, 2025 - Comments: 0

Moving data is one of the big challenges in the AI world. There is so much data being generated that even moving it back and forth from processors to memories requires a significant amount of power, enormous bandwidth, and frequently causes delays that can bog down performance. Now, with substantially more processing, different types of processors on each system on chip (SoC), and the emerging ... » read more

Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)

By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design" was published by researchers at Peter Grünberg Institute and Jülich Supercomputing Centre. Abstract "Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention s... » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)

By Technical Paper Link - 23 Apr, 2025 - Comments: 0

A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

Chiplet Tradeoffs And Limitations

By Ann Mutschler - 10 Apr, 2025 - Comments: 0

The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought. For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave indiv... » read more

Top-Down Vs. Bottom-Up Chiplet Design

By Ann Mutschler - 26 Nov, 2024 - Comments: 0

Chiplets are gaining widespread attention across the semiconductor industry, but for this approach to really take off commercially it will require more standards, better modeling technologies and methodologies, and a hefty amount of investment and experimentation. The case for chiplets is well understood. They can speed up time to market with consistent results, at whatever process node work... » read more

Chiplets Make Progress Using Interconnects As Glue

By Ann Mutschler - 31 Oct, 2024 - Comments: 0

Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

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tag: chiplet