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Author's Latest Posts


Analog Reliability Analysis for Mission-Critical Applications


Rapidly increasing electrical content in automobiles is driving the need for revolution in analog integrated circuit (IC) design methodology. Compared to designing for consumer electronics, designing for mission-critical applications—industrial, medical, space, and automotive—requires a different approach to reliability analysis. We will explore how reliability analysis needs to change for ... » read more

Accelerating SoC Time To Market With Cloud-Based Verification


This paper discusses the growing use of cloud and hybrid cloud environments among semiconductor design and verification teams. The schedule and efficiency benefits seen by verification teams using cloud are specifically highlighted, due to the considerable compute requirements associated with verification of advanced node SoCs, and the significant impact verification has on the overall SoC proj... » read more

Cadence Cloud—The Future Of Electronic Design Automation


Design complexity and competitive pressures are driving electronics developers to seek innovative solutions to gain competitive advantage. A key area of investigation is applying the power of the cloud to electronic design automation (EDA) to dramatically boost productivity. Grounded in its long history of providing hosted design solutions (HDS) and internal experience with cloud-based design, ... » read more

Improving Test Coverage And Eliminating Test Escapes Using Analog Defect Analysis


While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Backchannel Modeling And Simulation Using Recent Enhancements To The IBIS Standard


Recent enhancements to the upcoming IBIS standard now support backchannel training, enabling IBIS-AMI models to emulate this real-world SerDes behavior. AMI modelers now can incorporate backchannel algorithms into their IBIS-AMI models, automating the optimization of transmitter and receiver equalization settings in the same manner as their actual SerDes hardware devices. This saves system desi... » read more

Functional Safety Methodologies For Automotive Applications


Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies a... » read more

Meeting The Challenges Of The 2018 National Defense Strategy


In Secretary of Defense James Mattis’ Summary of the 2018 National Defense Strategy: Sharpening the American Military’s Competitive Edge, he provides a critical framework for driving “urgent change at significant scale.” This paper describes the role that Cadence can play in assisting the nation and its partners in achieving that urgency and scale of change called for in the vision and ... » read more

Functional Safety Methodologies For Automotive Applications


Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies a... » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces


As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm


Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

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