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Functional Safety Methodologies For Automotive Applications


Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies a... » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces


As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm


Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns


In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

Three Things You Need To Know To Use The Accellera PSS


Three primary considerations for adopting the Accellera Portable Stimulus Standard (PSS) are understanding the following: the value and relevance of this standard; the fundamental concepts of PSS modeling, including building blocks, process, and mindset; and PSS portability and how these scenarios can be applied to a specific platform. In this paper, we explore these three topics. To read mo... » read more

Efficient Verification Of Mixed-Signal SerDes IP Using UVM


Interface IP is an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal v... » read more

Modeling Of The Electrical Performance Of The Power And Ground Supply For A PC Microprocessor On A Card


The electrical characteristics of the power and ground supply of a PC microprocessor packaged in a Ball Grid Array (BGA) package mounted on a card are studied by dynamic electromagnetic field analysis. The effects of decoupling capacitors of different types and at different locations are investigated to achieve the objectives of low power and ground impedance and no or insignificant resonances ... » read more

Choosing The Right Superlinting Technology For Early RTL Code Signoff


No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for successful implementation. Traditional lint tools have become ineffective in evaluating RTL code for today’s larger, more complex designs. However, superlinting technology, such as the Cadence J... » read more

Save Time And Minimize Errors By Automating Co-Design And Co-Analysis Of Chips, PCBs, And Packages


Given the complexity of today’s chips, packages, and PCBs, designing each in isolation is no longer judicious. Cross-domain co-design and co-analysis are key to ensuring optimal performance, cost reduction, and faster time to market. Such capabilities are provided by the Cadence Virtuoso System Design Platform, which integrates IC design—including multiple heterogeneous die—into the Alleg... » read more

Choosing The Right Verification Technology For CDC-Clean RTL Signoff


Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains. Clock domain crossing (CDC) signals, those which traverse these domains, are often subject to metastability effects that can cause functional errors. Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify correct data transfer across clock domains. As a result... » read more

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