Author's Latest Posts


3D PCB Design And Analysis: ECAD/MCAD And Where They Converge


The design of a board and its ‘home’ are heavily interdependent. They require careful consideration to ensure everything will be in working order when your product is ultimately brought to market. Many designs have been derailed by conflicts between ECAD and MCAD. Something as simple as an improperly placed / communicated mounting hole can send your project into a tailspin of re-designs. ... » read more

5G NR Primer For Amplifier And Filter Design


This primer examines some of the challenges engineers face when designing filters and power amplifiers for 5G New Radio (NR) communication systems. See how the Cadence AWR Design Environment platform can be used to simulate amplifier and filter performance under 5G operating conditions. Click here to continue reading.     » read more

How ML Enables Cadence Digital Tools To Deliver Better PPA


Artificial intelligence (AI) and machine learning (ML) are emerging as powerful new ways to do old things more efficiently, which is the benchmark that any new and potentially disruptive technology must meet. In chip design, results are measured in many different ways, but common metrics are power (consumed), performance (provided), and area (required), collectively referred to as PPA. These me... » read more

Intelligent System Design


Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, system companies are increasingly designing their own semiconductor chips, and semiconductor companies are delivering software stacks, to enable substantial differentiation of their products. This trend started in mobile devices and is now moving into cloud computing, automotiv... » read more

Artificial Intelligence And Machine Learning Add New Capabilities to Traditional RF EDA Tools


This article features contributions from RF EDA vendors on their various capabilities for artificial intelligence and machine learning. AWR Design Environment software is featured and highlights the network synthesis wizard. Click here to continue reading. » read more

Rising To Meet The Thermal Challenge


Thermal effects on electrical performance have always existed; processor speed limits are set by thermal limits, and power has been a key concern for the mobile and datacenter markets for a decade. Increased electrical content logically generates more heat, which affects system performance. For example, in the automotive market, ADAS and infotainment systems are drastically increasing automotiv... » read more

Best Full-Flow PPA


In the past few years, Cadence revolutionized the way digital designers could solve their design challenges by revamping the entire digital tool suite with key enhancements such as integrated engines, massively parallel processing, and early signoff optimization, all delivering faster turnaround time and best-in-class power, performance, and area (PPA) optimization. In the era of FinFETs and ad... » read more

Computational Software


To power the technologies and products of the future, end-application system companies are increasingly designing the full stack of their solution. Some are even designing their own semiconductors, and optimizing the end-to-end solution across chips, packages, printed circuit boards (PCBs), software, and the entire system to meet demanding market requirements. This movement is driving a converg... » read more

Plan-Based Analog Verification Methodology


The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier ... » read more

Improving Test Coverage And Eliminating Test Ecapes Using Analog Defect Analysis


While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

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