tag: Univ. Grenoble Alpes

Chip Industry Technical Paper Roundup: March 26
By Linda Christensen - 26 Mar, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=209 /] Find last week's technical paper additions here. » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

Chip Industry’s Technical Paper Roundup: May 16
By Linda Christensen - 16 May, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=103 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Recent Developments in Neuromorphic Computing, Focusing on Hardware Design and Reliability
By Technical Paper Link - 08 May, 2023 - Comments: 0

A new technical paper titled "Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies" was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino. Abstract "The field of neuromorphic computing has been rapidly evolving in recent years, with an incre... » read more

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches
By Technical Paper Link - 23 May, 2022 - Comments: 0

New academic paper titled "Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution", from researchers at Univ. Grenoble Alpes, CEA-LIST. Abstract "This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, and co... » read more

MRAM: from STT to SOT, for security and memory
By Technical Paper Link - 30 Apr, 2019 - Comments: 0

Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the leading candidates for embedded memory convergence in advanced technology nodes. It is particularly adapted to low-power applications, requiring a decent level of performance. However, it also have interests for secured applications. The PRESENT cipher is a lightweight cryptographic algorithm targeting ultra... » read more

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