Chip Industry’s Technical Paper Roundup: May 16

Neuromorphic HW design; microarchitectures for heterogeneous superconducting quantum computers; CXL-centric server processors; entangled quantum circuits; ferroelectric tunnelFET; analog in-memory computing; inspecting circuit layout for HW trojans; EV battery degradation; wireless olfactory interface for VR; 28nm-HKMG-based FeFET for synaptic applications.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to
emerging technologies
Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino
Microarchitectures for Heterogeneous Superconducting Quantum Computers Pacific Northwest National Laboratory, Princeton University, University of Chicago, Rutgers University, MIT, Brookhaven National Laboratory, and Infleqtion.
A Case for CXL-Centric Server Processors Georgia Tech
Loophole-free Bell inequality violation with circuits ETH Zurich
Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor Lund University
28 nm high-k-metal gate ferroelectric field effect transistors based synapses- A comprehensive overview Fraunhofer-Institut für Photonische Mikrosysteme IPMS, Indian Institute of Technology Madras, and GlobalFoundries
Accelerating AI Using Next-Generation Hardware: Possibilities and Challenges With Analog In-Memory Computing Lund University and Ericsson Research
A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans University of Texas at Dallas and Qualcomm
Battery Degradation in Electric and Hybrid Electric Vehicles: A Survey Study Clemson University and Operation Technology Inc.
Soft, miniaturized, wireless olfactory interface for virtual reality City University of Hong Kong, Hong Kong Science Park, Beihang University, and others

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