Chip Industry Technical Paper Roundup: June 16


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads 🔗 University of Wisconsin-Madison, AMD Beyond Silicon: Materials, Mechanisms, and Methods for Physical Neural Computing 🔗 University of Lübeck, TU Hamburg InjectV: M... » read more

Fault Injection Framework Targets RISC-V Security Weak Spots


Researchers from Politecnico di Torino and CEA-List published a technical paper titled “InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment.” Abstract "Fault Injection Attacks (FIAs) are a significant threat to hardware security, capable of compromising systems by inducing malicious faults in computation or storage. Evaluating resilience against such attacks is chal... » read more

Chip Industry Technical Paper Roundup: May 19


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Micro-Transfer Printing on Silicon Photonics: Tutorial, Recent Progress and Outlook 🔗 Ghent U., imec Challenges and prospects of 2D electronics for future monolithic CFETs 🔗 SKKU, Hanyang U. et al. A Device-Physics-Informed Artific... » read more

Supporting Safety Requirements from RTL Exploration Through Implementation in Semiconductor Devices (Politecnico di Torino, Synopsys)


A new technical paper, "Early Functional Safety and PPA evaluation for faster digital design development," was published by researchers at Politecnico di Torino and Synopsys. Abstract "The use of semiconductor devices in safety-critical applications is increasing in both volume and complexity. Applications in markets such as automotive, data centers, and aerospace have dependability requi... » read more

Chip Industry Technical Paper Roundup: Dec. 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=497 /] Find more semiconductor research papers here. » read more

Comprehensive Performance Bound and Bottleneck Analysis Of Neuromorphic Accelerators (Harvard, Politecnico di Torino, Intel et al.)


A new technical paper titled "Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators" was published by researchers at Harvard University, Politecnico di Torino, Intel, LMU Munich, Accenture Labs, BootLoop AI, TU Delft and Wordly. Abstract "Neuromorphic accelerators offer promising platforms for machine learning (ML) inference by leveraging event-driven, spatially-expa... » read more

Chip Industry Technical Paper Roundup: August 26


New technical papers recently added to Semiconductor Engineering’s library: [table id=467 /] Find more semiconductor research papers here. » read more

Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes with High Core Density (Politecnico di Torino, imec et al.)


A new technical paper titled "Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes" was published by researchers at Politecnico di Torino, EPFL, National Technical University of Athens and imec. Abstract "This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), address... » read more

Chip Industry Week in Review


Lines are blurring between government and industry: On the heels of last week's resignation demand, Intel CEO Lip-Bu Tan met with President Trump on Monday, with the President later saying, "The meeting was a very interesting one. His success and rise is an amazing story."  Now, Bloomberg reports the Trump administration is in talks with Intel for the U.S. government to take a stake in th... » read more

Chip Industry Technical Paper Roundup: August 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=460 /] Find more semiconductor research papers here. » read more

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