Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures


A new technical paper titled “Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures” was published by researchers at National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente.


“Nowadays, various memory-hungry applications like machine learning algorithms are knocking “the memory wall”. Toward this, emerging memories featuring computational capacity are foreseen as a promising solution that performs data process inside the memory itself, so-called computation-in-memory, while eliminating the need for costly data movement. Recent research shows that utilizing the custom extension of RISC-V instruction set architecture to support computation-in-memory operations is effective. To evaluate the applicability of such methods further, this work enhances the standard GNU binary utilities to generate RISC-V executables with Logic-in-Memory (LiM) operations and develop a new gem5 simulation environment, which simulates the entire system (CPU, peripherals, etc.) in a cycle-accurate manner together with a user-defined LiM module integrated into the system. This work provides a modular testbed for the research community to evaluate potential LiM solutions and co-designs between hardware and software.”

Find the technical paper here. Published March 2023.

Su, Jia-Hui, Chen-Hua Lu, Andrea Coluccio, Jenq Kuen Lee, Marco Vacca, Marco Ottavi, and Kuan-Hsun Chen. “Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures.” arXiv preprint arXiv:2303.12128 (2023).

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