tag: National Tsing Hua University

A Flexible Cluster Tool Simulation Framework With Wafer Batch Dispatching Time Recommendation
By UMC - 19 Dec, 2023 - Comments: 0

The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulatio... » read more

Research Bits: Dec. 18
By Jesse Allen - 18 Dec, 2023 - Comments: 0

Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

Chip Industry’s Technical Paper Roundup: Apr. 10
By Linda Christensen - 10 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=92 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures" was published by researchers at National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente. Abstract "Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Tow... » read more

Technical Paper Round-up: June 14
By Linda Christensen - 14 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Finding Wafer Defects Using Quantum DL
By Technical Paper Link - 13 Jun, 2022 - Comments: 0

New research paper titled "Semiconductor Defect Detection by Hybrid Classical-Quantum Deep Learning" by researchers at National Tsing Hua University. Abstract "With the rapid development of artificial intelligence and autonomous driving technology, the demand for semiconductors is projected to rise substantially. However, the massive expansion of semiconductor manufacturing and the develo... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 13 Aug, 2021 - Comments: 0

Chipmakers and OEMs Samsung has announced its latest foldable smartphones--the Galaxy Z Fold3 5G and Galaxy Z Flip3 5G. The systems are based on Samsung’s 5nm application processor. One system is the company’s most affordable foldable phone. The Galaxy Z Fold3 is $1,799.99, while the Galaxy Z Flip3 is $999.99. Samsung also announced two smartwatches—the Galaxy Watch4 and Galaxy Watch4... » read more

Manufacturing Bits: March 2
By Mark LaPedus - 02 Mar, 2021 - Comments: 0

Next-gen AFM At the recent SPIE Advanced Lithography conference, Imec, Infinitesima and others described a new metrology tool technology called a Rapid Probe Microscope (RPM). Infinitesima has shipped its first RPM 3D system, enabling three-dimensional (3D) metrology applications for leading-edge chips. The system was jointly developed with Imec. In the IEDM paper, Imec and Infinitesima... » read more

Manufacturing Bits: July 21
By Mark LaPedus - 21 Jul, 2020 - Comments: 1

Intel’s next-gen MRAM At the recent 2020 Symposia on VLSI Technology and Circuits, Intel presented a paper on a CMOS-compatible spin-orbit torque MRAM (SOT-MRAM) device. Still in R&D, SOT-MRAM is a next-generation MRAM designed to replace SRAM. Generally, processors integrate a CPU, SRAM and a variety of other functions. SRAM stores instructions that are rapidly needed by the processo... » read more

Challenges For Compute-In-Memory Accelerators
By Katherine Derbyshire - 18 Jun, 2020 - Comments: 1

A compute-in-memory (CIM) accelerator does not simply replace conventional logic. It's a lot more complicated than that. Regardless of the memory technology, the accelerator redefines the latency and energy consumption characteristics of the system as a whole. When the accelerator is built from noisy, low-precision computational elements, the situation becomes even more complex. Tzu-Hsian... » read more

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