tag: National Tsing Hua University

Chip Industry Technical Paper Roundup: June 25
By Linda Christensen - 25 Jun, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=236 /] More ReadingTechnical Paper Library home » read more

ML Method To Predict IR Drop Levels
By Technical Paper Link - 21 Jun, 2024 - Comments: 0

A new technical paper titled "IR drop Prediction Based on Machine Learning and Pattern Reduction" was published by researchers at National Tsing Hua University, National Taiwan University of Science and Technology, and MediaTek. Abstract (partial) "In this paper, we propose a machine learning-based method to predict IR drop levels and present an algorithm for reducing simulation patterns, w... » read more

Chip Industry Technical Paper Roundup: June 18
By Linda Christensen - 18 Jun, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=234 /] More ReadingTechnical Paper Library home » read more

Device Characteristics of GAA-Structured CMOS and CTFET Under Varying Temperatures
By Technical Paper Link - 10 Jun, 2024 - Comments: 0

A new technical paper titled "Vertical-Stack Nanowire Structure of MOS Inverter and TFET Inverter in Low-temperature Application" was published by researchers at National Tsing Hua University and National United University in Taiwan. Abstract "Tunneling field effect transistors (TFET) have emerged as promising candidates for integrated circuits beyond conventional metal oxide semiconductor ... » read more

A Flexible Cluster Tool Simulation Framework With Wafer Batch Dispatching Time Recommendation
By UMC - 19 Dec, 2023 - Comments: 0

The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulatio... » read more

Research Bits: Dec. 18
By Jesse Allen - 18 Dec, 2023 - Comments: 0

Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

Chip Industry’s Technical Paper Roundup: Apr. 10
By Linda Christensen - 10 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=92 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures" was published by researchers at National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente. Abstract "Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Tow... » read more

Technical Paper Round-up: June 14
By Linda Christensen - 14 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Finding Wafer Defects Using Quantum DL
By Technical Paper Link - 13 Jun, 2022 - Comments: 0

New research paper titled "Semiconductor Defect Detection by Hybrid Classical-Quantum Deep Learning" by researchers at National Tsing Hua University. Abstract "With the rapid development of artificial intelligence and autonomous driving technology, the demand for semiconductors is projected to rise substantially. However, the massive expansion of semiconductor manufacturing and the develo... » read more

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