Chip Industry Technical Paper Roundup: Oct. 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=360 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


Global spending on 300mm fab equipment is expected to reach a record US$400 billion from 2025 to 2027, according to SEMI. Key drivers are the regionalization of semiconductor fabs and the increasing demand for AI chips in data centers and edge devices, with China, South Korea, and Taiwan leading the way. The Biden-Harris Administration launched the National Semiconductor Technology Center’... » read more

Hardware Acceleration Approach for KAN Via Algorithm-Hardware Co-Design


A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference" was published by researchers at Georgia Tech, TSMC and National Tsing Hua University. Abstract "Recently, a novel model named Kolmogorov-Arnold Networks (KAN) has been proposed with the potential to achieve the functionality of traditional deep neural networks (DNNs) using ... » read more

Chip Industry Technical Paper Roundup: June 25


New technical papers recently added to Semiconductor Engineering’s library. [table id=236 /] More ReadingTechnical Paper Library home » read more

ML Method To Predict IR Drop Levels


A new technical paper titled "IR drop Prediction Based on Machine Learning and Pattern Reduction" was published by researchers at National Tsing Hua University, National Taiwan University of Science and Technology, and MediaTek. Abstract (partial) "In this paper, we propose a machine learning-based method to predict IR drop levels and present an algorithm for reducing simulation patterns, w... » read more

Chip Industry Technical Paper Roundup: June 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=234 /] More ReadingTechnical Paper Library home » read more

Device Characteristics of GAA-Structured CMOS and CTFET Under Varying Temperatures


A new technical paper titled "Vertical-Stack Nanowire Structure of MOS Inverter and TFET Inverter in Low-temperature Application" was published by researchers at National Tsing Hua University and National United University in Taiwan. Abstract "Tunneling field effect transistors (TFET) have emerged as promising candidates for integrated circuits beyond conventional metal oxide semiconductor ... » read more

A Flexible Cluster Tool Simulation Framework With Wafer Batch Dispatching Time Recommendation


The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulatio... » read more

Research Bits: Dec. 18


Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

Chip Industry’s Technical Paper Roundup: Apr. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=92 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

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