Making Hybrid Bonding Better

Key Takeaways

• Fab processes are optimizing for cleanliness, planarity, and high bond quality.
• Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM.
• A thin, protective layer helps preserve the Cu/dielectric during aggressive processes.

The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipmakers are rethinking how devices are built, stacked, and powered.

Hybrid bonding is perhaps the biggest structural enabler of 3D integration, as it can achieve several orders of magnitude more interconnects than solder bumps in the same footprint, while improving signal and power integrity. It is essential to integrating multiple chiplets per package, and it decreases memory/processor latency while consuming less power.

This is the fastest-growing segment of advanced packaging, and Yole Group’s expects hybrid bonding equipment to grow by 21% CAGR between 2025 and 2030. Driven by intense demand for AI, high-performance computing, and other chiplet-based architectures, hybrid bonding enables high-bandwidth interconnections between chips with negligible signal loss.

Hybrid bonding already is being used in select high-end applications, but more work is needed to improve the quality of bond interfaces so that bonded copper interconnects behave as if they were fabricated on the same chip. This is a tall order considering the need for particle-free surfaces, nanometer-level copper dishing across 300mm wafers, and low wafer distortion to allow 50nm alignment precision between wafers.

Even so, progress in scaling hybrid bonding from today’s production chips with 9µm copper-copper connections to 2µm and below appears to be achievable using either wafer-to-wafer or die-to-wafer hybrid bonding. It is a constant on the roadmaps of all leading foundries.

Hybrid bonding started out as an elegant solution to increasing the brightness of CMOS image sensors. It now is enabling breakthroughs in SRAM/processor stacks for HPC and multi-tiered 3D NAND devices, and it is expected to enable more compact HBM modules, 3D DRAMs, and IoT devices in the future.

“Hybrid bonding is the pinnacle of fine-pitch packaging, minimizing resistance, parasitic capacitance-induced latency, and power consumption while improving thermal performance and bandwidth relative to microbump bonds,” said Jonathan Abdilla, director of technology at Besi.

Key developments underway
Hybrid bonding also struggles to meet the low thermal budget and cost-effectiveness required for high-bandwidth memory (HBM) stacks. As a result, the leading HBM makers — SK hynix, Micron, and Samsung — will likely remain with microbumps for HBM4. In addition, HBM requires lower-cost processing than is currently available with hybrid bonding, especially around long annealing steps, slow pick-and-place for die-to-die bonding, and long queue times between steps that can introduce damaging moisture to the bond interface.

One way to reduce the need for high-temperature processing is to deposit nanotwinned copper. Because of its preferred <111> grain orientation, NT copper is especially well-suited to fine-pitch hybrid bonding because it can be annealed at about 200°C.

“Copper-copper bonding is typically performed at about 400 degrees Celsius,” said Chee Ping Lee, technical director of heterogeneous integration at Lam Research. “But with nanocrystalline copper, the structure enables faster diffusion of these copper grains, so you can accomplish lower-temperature bonding.”

Aside from annealing, the PECVD process used to deposit the SiCN or SiO₂ dielectrics typically occurs at ~350°C. One potential answer involves sputtering of SiCN layers. Sputtering using a SiC target and nitrogen reactive gas can deposit SiCN below 250°C. [1]

Controlling contamination during processing is critical. Engineers are turning to plasma dicing to help drive down particulate levels during singulation. Plasma dicing is performed in a vacuum chamber where it removes material vertically through the wafer, rather than a mechanical blade or laser dicing, which produces greater quantities of silica dust and other debris. In addition, microcracks and die-edge chipping are much less likely to occur with plasma dicing processes.

Hybrid bonding is part of the industry’s larger move to plan early for 2.5D and 3D optimization, which also calls for multi-die co-design. “Hybrid bonding and 3D integration fundamentally shift chip design from a single‑die mindset to a true system‑level, multi-die co‑design approach, where logic, memory, and accelerators must be partitioned, analyzed, and optimized together as a vertically integrated stack,” said Lakshmi Jain, director of product management for I/O library IP at Synopsys.

This calls for holistic design based on the end system. “With hybrid bonding enabling extremely fine‑pitch, dense vertical interconnects, designers must rethink early architectural exploration, cross‑die floor-planning, power and thermal distribution, and die‑to‑die interface planning,” said Jain. “This increases the need for 3D‑aware timing analysis, extraction, verification, and signoff, as decisions made on one die directly affect performance, thermals, and reliability across the entire stack.”

Synopsys has developed an ultra-compact die-to-die I/O solution optimized for 2.5D, 3D, and SoIC packaging. “The I/O cells fit within hybrid bond bump pitches, enabling high bandwidth, low latency, and energy-efficient vertical interconnects between stacked dies,” Jain said.

In addition to shifting how design for manufacturing is performed, hybrid bonding requires tighter integration among fab tools such as copper fill and CMP, and pick-and-place and annealing. This is because all the steps that precede bonding tend to impact the condition of the incoming wafer in terms of distortion, warpage control, and across-wafer uniformity, which significantly impact overlay results, yield, and reliability.

Which hybrid bonding flow is best?
There are numerous electrical benefits associated with replacing microbumps with hybrid bonding, including lower resistance, capacitance, and power consumption. “Hybrid bonding improves both electrical performance and power efficiency by significantly minimizing parasitics compared to bonding with microbumps,” said Bernd Dielacher, director of business development at EV Group.

By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. In fact, in HBM processes, adoption may be less driven by the need for greater I/O density than by vertical size. “Yes, hybrid bonding can enable higher interconnect density for sure, but the key driver in high bandwidth memory is the thickness reduction by eliminating the bumps between multiple DRAMs,” said Lam Research’s Lee.

The wafer-to-wafer (W2W) approach to hybrid bonding has a proven track record of success ever since Sony first utilized it for CMOS image sensors more than a decade ago. Already, researchers have demonstrated 400nm bonding. But W2W has two serious limitations. The dies must be identical in size, and there is no opportunity to remove non-yielding die from the bonding process.

That’s where die-to-wafer bonding comes in (see Table 1). Only known-good dies are bonded, and dies of any size can be used. Relatively speaking, W2W is more mature than die-to-wafer, and it meets tighter specifications for overlay and precision. For example, the industry has demonstrated 400nm wafer-to-wafer bonding while die-to-wafer bonding has reached 2µm pitch in R&D (see Figure 2).

Table 1: Comparing wafer-to-wafer and die-to-wafer bonding. Source: Laura Peters/Semiconductor Engineering

How the process works
The key factors behind achieving quality hybrid bonding include:

• Engineering defect-free atomic contact across thousands (or millions) of tiny interfaces at once;
• Minimizing wafer bow or warpage;
• Achieving full planarity after CMP with no topography differences (0.5nm RMS) because CMP results are the foremost determinant of bond yield;
• Zero particles or residues on the bonding surface;
• Immediate bonding after activation, which prevents contamination and moisture damage;
• High alignment accuracy (200nm to 50nm, depending on feature size), which prevents opens and shorts, and
• Tight pick-and-place die placement precision (below 5µm pitch requires 100nm overlay).

The wafer-to-wafer hybrid bonding process begins with two device wafers already processed through the final back-end-of-line (BEOL) interconnect level. Plasma-enhanced CVD typically deposits a suitable dielectric (SiO₂ or SiCN), followed by reactive ion etch to form the vias that will contain the copper pads. SiCN is known for its high bonding strength and good copper-barrier properties.

To prevent copper diffusion into the dielectric, a barrier metal (TaN) is deposited by CVD or ALD, followed by copper seed ALD and then copper plating. Copper pads are ideally square. Copper CMP then polishes down to the dielectric level, leaving slight copper dishing (several nm) below the planar feature. That minuscule gap will be filled when the copper expands upon annealing.

Fig. 1: Wafer-to-wafer hybrid bonding process flow. Source: EV Group

Next, a megasonic wafer cleaning removes all debris from the wafer surface. Then, the plasma process (typically in N₂) activates the exposed dielectric to form a high concentration of reactive sites (-OH), thereby increasing its adhesive properties. Surface activation is critical because the hybrid bonding process is driven by surface chemistry, unlike thermocompression bonding, which is pressure- and temperature-driven.

Following a short queue time (longer for die-to-wafer processes), the two wafers are aligned (using IR light) and brought into intimate contact in the wafer bonder. Then the bond-front progresses rapidly across the entire wafer at room temperature.

“All hybrid bonding processes (D2W, coD2W and W2W) have in common that they require proper alignment (depending on the copper pitch),” said Thomas Schmidt, product manager of permanent wafer bonding at Suss. “Alignment must be even better than 100nm, sometimes even 50nm. The alignment must not only be accurate, but also precise (repeatable from bond to bond).”

“Prior to bonding, optimized CMP processes for surface planarization and controlled dishing of copper pads are key,” said EV Group’s Dielacher. “Essential for the successful bonding process itself is advanced process control, such as adaptation to incoming wafer variations, distortion control, and the implementation of feedback loops with data from metrology tools or lithography scanners.”

Dielacher emphasized the importance of good stability in bonding equipment, which determines repeatability, as well as particle control during bonding. “Particle control inside the equipment includes air flow management, the use of mini-environments, and optimized substrate handling. In addition, in-situ process monitoring can help further reduce particle contamination,” he said.

Others emphasize the importance of CMP. “CMP is the most critical step for hybrid bonding. It needs to ensure that the copper dishing is uniform throughout the entire wafer, from center to edges,” said Besi’s Abdilla. “We typically look at 5nm dishing or below. While controlling copper dishing, CMP needs to ensure that the dielectric is not eroded too much. Otherwise, the barrier layer around the bond pad will become exposed, thus preventing bonding from happening.”

After bonding, the wafer stack undergoes high-temperature annealing (~350°C), causing the dielectric to convert hydrogen bonds to strong covalent bonds while the copper fuses together and makes electrical contact. This process is called face-to-face bonding, though face-to-back bonding processes are now available to stack more than two wafers. Acoustic microscopy can check the quality of the bond. Voids will appear as white specs, whereas a void-free bond results in a black acoustic microscopy image.

To help protect the bonding interface, imec research led by Ye Lin recently proposed the deposition of a thin inorganic protective layer to shield the bond area from the effects of water, slurries, and chemistry during temporary bonding to carrier with adhesives, wafer thinning/CMP/etching, die singulation, and cleaning steps. [2] The protective layer, when combined with a laser release layer, can facilitate removal of the die from the carrier during pick-and-place of die to wafer.

“One of the major challenges remaining [for 2µm die-to-wafer bonding] is the degradation of die bonding surface during the die preparation and possibly staging time before assembly,” said the imec team. In this example of 2-micron copper-copper pitch, the protective layer helped maintain a small copper recess level of 2nm.

Fig. 2: 2 micron pitch bonds completed using die-to-wafer hybrid bonding. Source: imec

Any protective layer needs to be transparent to alignment marks and cleanly removed prior to bonding. Importantly, the imec group improved the die-to-wafer overlay by comparing iterations of test materials, using a feedback loop between the overlay metrology tool and the die bonder. This reduced the translational errors. Scaling errors were reduced by engineering the dielectric layer for reduced warpage and by using a variety of alignment mark shapes. In addition to maintaining copper recess, the study showed fewer voids formed between the reconstituted dies and wafer.

A key advantage of an inorganic release layer is its compatibility with higher process temperatures. “Based on silicon carriers and inorganic release layers of nanometer-precise thickness, the technology enables high-temperature processing and ultrathin layer transfer with thicknesses well below what traditional debonding technologies support,” said Dielacher. “Therefore, the fully front-end compatible technology enables completely new process flows in 3D-IC and 3D sequential integration schemes.”

One key issue with long queue times between hybrid CMP and wafer bonding is moisture absorption, which weakens the bond interface and corrodes copper pads. Queue times of several hours can occur during the process of gathering wafers together for the batch anneal step. Using thermal cycling and aging stress tests, engineers from Applied Materials assessed the electrical yield of 50µm dies placed on wafers and singulated using plasma dicing. Xiao Dong Chen and colleagues found that a sacrificial TiN layer maintained the copper dishing profile while eliminating die-edge delamination associated with thin die warpage. [3] Kelvin contact resistance measurements at the die edges remained within specification when the TiN was used.

Even though temporary bonding and debonding (TBDB) are not required in hybrid bonding, they typically are used for wafer thinning, and therefore part-and-parcel of 3D stacking processes. “The current challenges in TBDB are mainly focused on improving the total thickness variation after coating of the temporary bonding material (TBM). Temporary bonding and debonding are mainly needed for substrate thinning, in general, to allow thin dies (<100µm or even <50µm),” said Suss’ Schmidt. “At the wafer level, such a thickness has disadvantages, critical for handling, and therefore W2W bonding applications. For D2W, however, handling of thin dies is more feasible, and there is a clear trend down to 50µm and less to allow future memory stacks, such as in high-bandwidth memory.”

Defectivity control in die-to-wafer bonding
Controlling defectivity at the bonding interface is one of the most critical challenges in D2W hybrid bonding. That control begins with a Class 3 or better cleanroom environment.

Any particles on the dielectric/copper surface can cause clustered open defects and debonded sections on the wafer. Surface particles can cause voids several times larger than the size of the original particle.

Besi’s Abdilla suggested strategies for controlling defectivity inside tools, especially the pick-and-place tool:

• Use sophisticated mini-environments that protect material from outside influence, but also adverse effects within the machine;
• Strategically develop a back-end clean supply chain (common in the front-end);
• Establish knowledge transfer and training programs for clean design and operation;
• Use metrology commonly found in the front end (< 100 nm particles), like SEM/EDX during test setup to track defects, and
• Properly design machines and parts for low surface roughness such as suppressed abrasion of moving parts.

“When bonding at nanometer level accuracy, all vibrations and other involuntary movements from the bonder play a big role. The target should be that upon initial contact of the die with the substrate wafer, there is adherence. This locks the die in place and avoids die-center bonding inaccuracy,” said Abdilla.

Conclusion
Hybrid bonding is an essential capability that enables chip stacking by joining wafers or dies at fine metal pitch (<10µm), rather than using solder bumps, which currently enable a 30-35µm pitch. Wafer-to-wafer hybrid bonding is proven in manufacturing for CMOS image sensors, SRAM/processor chips, and 3D NAND devices. Equipment manufacturers and foundries are collaborating to increase process throughput and shorten queue times between activation and bonding steps. Sacrificial inorganic films, such as TiN, may play an increasing role in keeping dielectric and copper pad surfaces clean during various assembly processes, including wafer thinning, wafer cleaning, and die singulation.

In preparation for hybrid bonding adoption for HBM, low-thermal-budget films such as sputtered SiCN or nanotwinned copper that anneals at lower temperature may gain popularity, though more reliability studies are needed for production adoption.

References

1. Choi, S. Lee, S. Park and S. E. Kim, “Evaluation of PVD SiCN for Cu/SiCN Hybrid Bonding,” 2024 International Conference on Electronics Packaging (ICEP), Toyama, Japan, 2024, pp. 305-306, doi: 10.23919/ICEP61562.2024.10535604.
2. Lin et al., “2 μm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation,” 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, TX, USA, 2025, pp. 272-276, doi: 10.1109/ECTC51687.2025.00054.
3. D. Chen et al., “Integration Solution for Thin D2w Hybrid Bonding for Yield and Reliability,” 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, TX, USA, 2025, pp. 33-36, doi: 10.1109/ECTC51687.2025.00011.

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