Sidestepping Moore’s Law

By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Power, Reliability And Security In Packaging

By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

HBM2e Offers Solid Path For AI Accelerators

By Sanjay Charagulla - 13 Jun, 2019 - Comments: 0

Today, AI processors are so blazingly fast that they’re constantly having to wait for data from memory. Unfortunately, with the status quo, memory is just not fast enough to unleash the true performance of those new and highly advancing AI processors. In simple terms, AI processor performance is rapidly growing, and memory is not keeping up. This creates a bottleneck, or what Rambus calls the... » read more

Memory Options And Tradeoffs

By Ed Sperling - 13 Jun, 2019 - Comments: 0

Steven Woo, Rambus fellow and distinguished inventor, talks with Semiconductor Engineering about different memory options, why some are better than others for certain tasks, and what the tradeoffs are between the different memory types and architectures. Related Articles/Videos Memory Tradeoffs Intensify In AI, Automotive Applications Why choosing memories and archi... » read more

HBM2 Vs. GDDR6: Tradeoffs In DRAM

By Ed Sperling - 13 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to talk about new DRAM options and considerations with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allen, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of th... » read more

Speeding Up AI

By Ed Sperling - 06 Jun, 2019 - Comments: 0

Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to talk about AI, which processors work best where, and different approaches to accelerate performance. SE: How is AI affecting the FPGA business, given the constant changes in algorithms and the proliferation of AI almost everywhere? Blake: As we talk to more and more customers deploying new products and... » read more

CEO Outlook: It Gets Much Harder From Here

By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Latency Under Load: HBM2 vs. GDDR6

By Ed Sperling - 09 May, 2019 - Comments: 0

Steven Woo, Rambus fellow and distinguished inventor, explains why data traffic and bandwidth are critical to choosing the type of DRAM, options for improving traffic flow in different memory types, and how this works with multiple memory types. Related Video GDDR6 - HBM2 Tradeoffs Why designers choose one memory type over another. Applications for each were clearly delineate... » read more

Focus Shifting From 2.5D To Fan-Outs For Lower Cost

By Ed Sperling - 29 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

More Memory And Processor Tradeoffs

By Ed Sperling - 11 Apr, 2019 - Comments: 0

Creating a new chip architecture is becoming an increasingly complex series of tradeoffs about memories and processing elements, but the benefits are not always obvious when those tradeoffs are being made. This used to be a fairly straightforward exercise when there was one processor, on-chip SRAM and off-chip DRAM. Fast forward to 7/5nm, where chips are being developed for AI, mobile ph... » read more

← Older posts

tag: HBM