tag: HBM

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Steffora Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

ML Opening New Doors For FPGAs
By Bryon Moyer - 24 Jun, 2020 - Comments: 0

FPGAs have long been used in the early stages of any new digital technology, given their utility for prototyping and rapid evolution. But with machine learning, FPGAs are showing benefits beyond those of more conventional solutions. This opens up a hot new market for FPGAs, which traditionally have been hard to sustain in high-volume production due to pricing, and hard to use for battery-dri... » read more

The Next Advanced Packages
By Mark LaPedus - 18 Jun, 2020 - Comments: 2

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

The Good And Bad Of Chiplets
By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Rising Packaging Complexity
By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

‘More Than Moore’ Reality Check
By Ann Steffora Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

An Inside Look At Testing’s Leading Edge
By Ed Sperling - 12 May, 2020 - Comments: 0

Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

Reliability Monitoring Of GUC 7nm High-Bandwidth Memory (HBM) Subsystem
By proteanTecs - 27 Apr, 2020 - Comments: 0

This white paper presents the use of proteanTecs’ Proteus for HBM subsystem reliability based on deep data analytics and enhanced visibility, overcoming the limitations of advanced heterogeneous packaging. It will describe the operation concept and provide results from a GUC 7nm HBM Controller ASIC. A typical CoWoS chip has hundreds of thousands of micro-bumps (u-bumps). 3-8 u-bumps are us... » read more

DDR PHY Training
By Ed Sperling - 21 Apr, 2020 - Comments: 0

Brett Murdock, senior product marketing manager at Synopsys, explains how to train the DRAM physical layer using firmware, why that is so important for flexibility, and what kinds of issues engineers encounter when using this approach. » read more

2.5D Architecture Answers AI Training’s Call for “All of the Above”
By Frank Ferro - 09 Apr, 2020 - Comments: 0

The impact of AI/ML grows daily impacting every industry and touching the lives of everyone. In marketing, healthcare, retail, transportation, manufacturing and more, AI/ML is a catalyst for great change. This rapid advance is powerfully illustrated by the growth in AI/ML training capabilities which have since 2012 grown by a factor of 10X every year. Today, AI/ML neural network training mod... » read more

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