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tag: HBM

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Steffora Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

On the Road To Higher Memory Bandwidth
By Frank Ferro - 09 Sep, 2021 - Comments: 0

In the decade since HBM was first announced, we’ve seen two-and-a-half generations of the standard come to market. HBM’s “wide and slow” architecture debuted first at a data rate of 1 gigabit per second (Gbps) running over a 1024-bit wide interface. The product of that data rate and that interface width provided a bandwidth of 128 gigabytes per second (GB/s). In 2016, HBM2 doubled the s... » read more

Will Monolithic 3D DRAM Happen?
By Bryon Moyer - 09 Sep, 2021 - Comments: 1

As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

Sweeping Changes Ahead For Systems Design
By Ann Steffora Mutschler - 29 Jul, 2021 - Comments: 0

Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources. Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so ma... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Advanced Packaging’s Next Wave
By Mark LaPedus - 20 May, 2021 - Comments: 0

Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

HBM Takes On A Much Bigger Role
By Brian Bailey - 13 May, 2021 - Comments: 1

High-bandwidth memory is getting faster and showing up in more designs, but this stacked DRAM technology may play a much bigger role as a gateway for both chiplet-based SoCs and true 3D designs. HBM increasingly is being viewed as a way of pushing heterogenous distributed processing to a completely different level. Once viewed as an expensive technology that only could be utilized in the hig... » read more

Next-Gen Design Challenges
By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

New Uses For AI
By Ed Sperling - 01 Apr, 2021 - Comments: 0

AI is being embedded into an increasing number of technologies that are commonly found inside most chips, and initial results show dramatic improvements in both power and performance. Unlike high-profile AI implementations, such as self-driving cars or natural language processing, much of this work flies well under the radar for most people. It generally takes the path of least disruption, b... » read more

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