tag: HBM

AI Accelerators Usher In New Era For IC Test
By Laura Peters - 07 Apr, 2026 - Comments: 0

Key Takeaways The parallelism in AI accelerators enables low latency but complicates failure isolation. HBM can account for 50% of package cost, so known-good stack assurance is critical. DFT and test cooperate to solve final test, singulated die test, SLT, and in-system test for data centers. AI accelerators are used for everything from training large language models to mak... » read more

HBM4E Raises The Bar For AI Memory Bandwidth
By Nidish Kamath - 12 Mar, 2026 - Comments: 0

The pace of AI innovation continues to expose a painful reality. Compute keeps scaling, but memory bandwidth remains one of the hardest bottlenecks to remove. As AI models grow larger and more complex, feeding data fast enough into accelerators has become just as critical as raw compute capability. High Bandwidth Memory (HBM) has been central to solving this challenge, and the next step in that... » read more

RPU: A Chiplet-Based Architecture To Address The Challenges of the Modern Memory Wall (Harvard University)
By Technical Paper Link - 04 Mar, 2026 - Comments: 0

Researchers from Harvard University have released “RPU -- A Reasoning Processing Unit”. Abstract “Large language model (LLM) inference performance is increasingly bottlenecked by the memory wall. While GPUs continue to scale raw compute throughput, they struggle to deliver scalable performance for memory bandwidth bound workloads. This challenge is amplified by emerging reasonin... » read more

Making Hybrid Bonding Better
By Laura Peters - 02 Mar, 2026 - Comments: 0

Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Router-in-a-Package Design Combining HBM4, Chiplets and In-Package Optics (Technion, Berkeley, UCSD)
By Technical Paper Link - 18 Feb, 2026 - Comments: 0

A new technical paper "Scaling Routers with In-Package Optics and High-Bandwidth Memories" was posted by researchers at Technion, UC Berkeley and UC San Diego. Abstract "This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optic... » read more

AI Inference Needs A Mix-And-Match Memory Strategy
By Raj Uppala - 12 Feb, 2026 - Comments: 0

AI inference is no longer a single workload that can be served efficiently by a single type of accelerator or memory. From fast chat replies to 10M token codebases, inference spans wildly diverse workloads with very different limits on latency, bandwidth, capacity, and compute, as the figure below demonstrates.1 Source: Meta1 The AI inference spectrum of workloads includes: Inter... » read more

Automated High-Speed Interface Routing in Multi-Die Designs
By Synopsys - 28 Jan, 2026 - Comments: 0

2.5D and 3D Multi-die design is revolutionizing chip integration by enabling thousands of high-speed connections between dies (also called chiplets). Discover how close placement of dies boosts bandwidth, minimizes latency, and maximizes data throughput. Read this white paper to find out about the importance of interconnectivity planning and die-to-die signal routing for successful m... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding
By Bryon Moyer - 13 Jan, 2026 - Comments: 0

The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

Four Architectural Opportunities for LLM Inference Hardware (Google)
By Technical Paper Link - 09 Jan, 2026 - Comments: 0

A new technical paper titled "Challenges and Research Directions for Large Language Model Inference Hardware" was published by Google. Abstract "Large Language Model (LLM) inference is hard. The autoregressive Decode phase of the underlying Transformer model makes LLM inference fundamentally different from training. Exacerbated by recent AI trends, the primary challenges are memory and in... » read more

Study Of HW Acceleration for Neural Networks (Arizona State Univ.)
By Technical Paper Link - 02 Jan, 2026 - Comments: 0

A new technical paper titled "Hardware Acceleration for Neural Networks: A Comprehensive Survey" was published by researchers at Arizona State University. Abstract "Neural networks have become a dominant computational workload across cloud and edge platforms, but their rapid growth in model size and deployment diversity has exposed hardware bottlenecks that are increasingly dominated by mem... » read more

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