tag: HBM

Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)
By Technical Paper Link - 01 Jan, 2026 - Comments: 0

A new technical paper titled "Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference" was published by researchers at Rensselaer Polytechnic Institute, ScaleFlux and IBM T.J. Watson Research Center. Abstract "LLM inference is increasingly memory bound, and HBM cost per GB dominates system cost. Current HBM stacks include short on-die ECC that tightens binning, raise... » read more

Chip Industry’s Top Videos 2025
By The SE Staff - 30 Dec, 2025 - Comments: 0

Rising complexity, new architectures, and AI's permeation of nearly everything left engineers struggling to keep up in 2025, as evidenced by this year's viewership numbers. Among the hottest topics were verification, agentic AI, DRAM/HBM, optimization of data movement, chiplets, and heterogeneous integration, but there was steady traffic growth across all sectors. Top 10 most-watched videos ... » read more

High Bandwidth Memory (HBM): Everything You Need To Know
By Rambus - 12 Nov, 2025 - Comments: 0

In an era where data-intensive applications, from AI and machine learning to high-performance computing (HPC) and gaming, are pushing the limits of traditional memory architectures, High Bandwidth Memory (HBM) has emerged as a high-performance, power-efficient solution. As industries demand faster, higher throughput processing, understanding HBM’s architecture, benefits, and evolving role in ... » read more

AI Memory: Enabling The Next Era Of High-Performance Computing
By Tadashi Oda - 11 Nov, 2025 - Comments: 0

The rapid advancement of artificial intelligence (AI) is driving unprecedented demand for high-performance memory solutions. AI-driven applications are fueling significant year-over-year growth in high-bandwidth memory (HBM). However, as AI models grow in complexity—from large language models (LLMs) to real-time inference applications—the need for faster, higher-bandwidth, and energy-effici... » read more

HBM Leads The Way To Defect-Free Bumps
By Laura Peters - 11 Nov, 2025 - Comments: 0

High-bandwidth memory stands at the forefront of multiple technology developments as a critical enabler of AI, but it is one of the most difficult modules to manufacture. Leading HBM device makers and foundries must simultaneously handle multi-layer chip stacking, die warpage, and shorter product lifecycles that are shrinking from two years down to just one. But perhaps the most formidable c... » read more

China GenAI: Who Will Fill The Vacuum?
By Geoff Tate - 10 Nov, 2025 - Comments: 1

China and the U.S.A are locked in a titanic battle over tariffs. The U.S. makes the world’s best AI Accelerators: Nvidia, AMD, Google, AWS …among others. But the U.S. worries China could deploy these for military purposes, so it imposed strict export controls that resulted in China getting the second-best AI accelerators. These export controls have been further tightened as part of tarif... » read more

Algorithm–HW Co-Design Framework for Accelerating Attention in Large-Context Scenarios (Cornell)
By Technical Paper Link - 07 Nov, 2025 - Comments: 0

A new technical paper titled "LongSight: Compute-Enabled Memory to Accelerate Large-Context LLMs via Sparse Attention" was published by researchers at Cornell University. Abstract "Large input context windows in transformer-based LLMs help minimize hallucinations and improve output accuracy and personalization. However, as the context window grows, the attention phase increasingly dominates... » read more

LPDDR6: Not Just For Mobile Anymore
By Ed Sperling - 03 Nov, 2025 - Comments: 0

LPDDR memory has been almost synonymous with mobile devices, but starting with the new LPDDR6 specification released in July 2025 by JEDEC, it will begin showing up inside of data centers, as well, early next year. The key factors in various flavors of DRAM are bandwidth, capacity, and cost. HBM is the fastest, but it's also expensive, and it requires a 2.5D or 3.5D packaging approach. GDDR is ... » read more

Critical Factors For Storing Data In DRAM
By Ed Sperling - 27 Oct, 2025 - Comments: 0

DRAM is becoming more complicated to develop, and more difficult to manage inside AI data centers. In the past, latency, bandwidth, and capacity were the primary considerations. But as the amount of data that needs to be processed, moved, and stored continues to rise, a whole new set of factors is emerging. Steven Woo, fellow and distinguished inventor at Rambus, talks about latency under load,... » read more

3D Stacked HBM and Accelerators for LLMs: Heat Management and PDN (Georgia Tech, SK Hynix)
By Technical Paper Link - 17 Oct, 2025 - Comments: 0

A new technical paper titled "3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency" was published by a researcher from Georgia Institute of Technology and SK Hynix. Abstract "Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures such as 2.5D integration of... » read more

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