HBM-Enabled FPGA-Based Graph Processing Accelerator


A technical paper titled "ACTS: A Near-Memory FPGA Graph Processing Framework" was published by researchers at University of Virginia and Samsung. Abstract: "Despite the high off-chip bandwidth and on-chip parallelism offered by today's near-memory accelerators, software-based (CPU and GPU) graph processing frameworks still suffer performance degradation from under-utilization of available ... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature


A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

Where Power Is Spent In HBM


HBM is gaining ground because of a spike in the amount of data that needs to be processed quickly, but big reductions in power are possible if that processing can be moved closer to the HBM modules, and if more can be done in each compute cycle without sending data back and forth to memory as frequently. Steven Woo, fellow and distinguished engineer at Rambus, talks about what can be done to bo... » read more

Choosing The Correct High-Bandwidth Memory


The number of options for how to build high-performance chips is growing, but the choices for attached memory have barely budged. To achieve maximum performance in automotive, consumer, and hyperscale computing, the choices come down to one or more flavors of DRAM, and the biggest tradeoff is cost versus speed. DRAM remains an essential component in any of these architectures, despite years ... » read more

The Path To Known Good Interconnects


Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Design And Verification Methodologies Breaking Down


Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

Choosing The Right Memory At The Edge


As the amount of data produced by sensors in cars and phones continues to grow, more of that data needs to be processed locally. It takes too much time and power to send it all to the cloud. But choosing the right memory for a particular application requires a series of tradeoffs involving cost, bandwidth, power, which can vary greatly by device, application, and even the data itself. Frank Fer... » read more

Adapting To Broad Shifts Essential In 2022


Change creates opportunity, but not every company is able to respond quickly enough to take advantage of those opportunities. Others may respond too quickly, before they properly understand the implications. At the start of a typical year, optimism is in plentiful supply. Any positive trend is seen as continuing, and any negative is seen as turning around. Normally the later in the year that... » read more

Boosting Data Center Memory Performance In The Zettabyte Era With HBM3


We are living in the Zettabyte era, a term first coined by Cisco. Most of the world’s data has been created over the past few years and it is not set to slow down any time soon. Data has become not just big, but enormous! In fact, according to the IDC Global Datasphere 2022-2026 Forecast, the amount of data generated over the next 5 years will be at least 2x the amount of data generated over ... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes


Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

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