Chip Industry Week In Review

By The SE Staff - 24 Jul, 2026 - Comments: 0

Notable deals Amkor and Nvidia signed a $1.5B multiyear agreement to develop advanced packaging and test technologies for next-gen AI and accelerated-computing platforms. Nvidia’s prepayment will support Amkor’s U.S. capacity expansion in Arizona, including high-density interconnect and heterogeneous integration capabilities. Siemens announced plans to acquire two EDA companies: D... » read more

From Highways To Health Care: Portability Proves Key To Physical AI

By Laura Peters - 22 Jul, 2026 - Comments: 0

Key Takeaways: Hyperspectral imaging is making a difference in surgery, disease diagnostics, and water conservation. Inverse lithography technology (ILT) finds a new application in reticle stitching. Leaders are porting learnings from the Automotive Chiplet Program to the Autonomous Edge Chiplet Program. With a healthy boost from AI and high-performance compute, medical devi... » read more

Chip Industry Week In Review

By The SE Staff - 17 Jul, 2026 - Comments: 0

Advanced manufacturing, packaging Intel Foundry will invest €5B to expand Intel 3 capacity at its Leixlip, Ireland campus. The company also entered high-volume manufacturing for a subset of Panther Lake processors manufactured on its 18A using ASML’s High-NA EUV technology. UMC delivered the first production wafers for SILITH’s 1.6T silicon photonics platform from its 300mm Singa... » read more

Data Center AI Growth Faces Challenging Bottlenecks

By Geoff Tate - 06 Jul, 2026 - Comments: 0

AI is rocketing ahead. It is the biggest industrial revolution of our age. AI adoption is growing, but still most are at early stages of learning. Anthropic, the leading frontier model provider with an annualized revenue run rate (ARR) of ~$47 billion with OpenAI close behind at ~$30 billion (Forbes). Google Gemini revenues aren’t broken out but Google Gemini processes over 3.2 quadrillion... » read more

Creating A Moore’s Law For AI Scaling

By Laura Peters - 24 Jun, 2026 - Comments: 0

Key Takeaways: AI scalability will require full-stack co-optimization, not just bigger data centers. AI workloads require a 10X compute efficiency gain over 10 years, making collaboration across algorithms, architectures, devices, packaging, and communication fabrics essential to deliver a 10X improvement in compute efficiency over the next decade. Edge AI chips are moving to leadi... » read more

How To Build Billions of Bumps

By Bryon Moyer - 18 Jun, 2026 - Comments: 0

Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

Chip Industry Technical Paper Roundup: June 16

By - 16 Jun, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads 🔗 University of Wisconsin-Madison, AMD Beyond Silicon: Materials, Mechanisms, and Methods for Physical Neural Computing 🔗 University of Lübeck, TU Hamburg InjectV: M... » read more

Modeling Multi-GPU Traffic For Distributed AI Workloads (UW Madison, AMD)

By - 15 Jun, 2026 - Comments: 0

Researchers from University of Wisconsin-Madison and AMD Research and Advanced Development published a technical paper titled “Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads.” Abstract: “As distributed AI workloads grow in scale, multi-GPU systems have become essential for training large models. Although techniques like kernel fusion and overlapping... » read more

Chip Industry Week In Review

By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Chip Industry Technical Paper Roundup: Jun. 2

By Linda Christensen - 02 Jun, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Physical Foundation Models: Fixed HW implementations of large-scale neural networks 🔗 Yale University, Cornell University, Boston University, NTT Research Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Princip... » read more

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tag: AMD

Chip Industry Week In Review

From Highways To Health Care: Portability Proves Key To Physical AI

Chip Industry Week In Review

Data Center AI Growth Faces Challenging Bottlenecks

Creating A Moore’s Law For AI Scaling

How To Build Billions of Bumps

Chip Industry Technical Paper Roundup: June 16

Modeling Multi-GPU Traffic For Distributed AI Workloads (UW Madison, AMD)

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: Jun. 2

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