Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Key Takeaways:
Chiplets are changing more than just architectures. They are changing the way chips get built.
As the industry moves from planar SoCs to multi-die systems, the engineering challenges no longer end at the edge of a single die. Performance, reliability, and yield now depend on how multiple dies behave together inside an advanced package, how data is prioritized and moved using a combination of interconnect technologies, and the impact of increasingly open ecosystems.
Chiplets are forcing a fundamental rethink of the entire design flow. Linear development methods are no longer sufficient when design, verification, packaging, test, and reliability decisions all influence one another from the start. Experts agree that success in the chiplet era depends on structured workflows that connect modeling, analysis, verification, and manufacturing decisions early — before expensive problems are locked in at tape-out or assembly. Why do those workflows matter? What must they include? How is AI beginning to make them more effective?
“There’s a lot of complexity when it comes to advanced packaging, 2.5D and 3D architectures, and there is a shift in the way companies work,” observed Andras Vass-Vernai, 3D-IC solution architect for thermal management and reliability at Siemens EDA. “A few years ago, packaging was very important for reliability. At a conference some years ago, somebody was boasting that the only reason everybody’s getting the latest gadgets and mobile phones is miniaturization, which was possible because some mechanical engineers figured out thermal management. But the way they did that was always somehow in a very siloed approach. They never really worked together with the chip designers and the electrical designers of the package. They were trading all kinds of specifications and design goals, and everybody was just trying to act on those. Advanced packaging has changed this because you need to understand very early on whether you’re making the right decisions or not.”
There are many considerations when it comes to the chiplet workflow, and perspectives vary based on where you sit in the semiconductor ecosystem. “When it comes to our traditional, monolithic view of ASIC design, we consider that 2D, and when you come to chiplets, it’s 2.5D and 3D because it’s layered,” noted Prem Theivendran, director of software engineering at Expedera. “The majority of the problems stem from the interconnects, and this is a big nightmare for whoever is doing this. There are also mechanical issues, electro-mechanical issues, electro-thermal issues, and signal integrity issues. The modeling for those three together is a multi-physics issue.”
As an IP design house, Expedera doesn’t create models, but it has looked at this for some chiplet customers. “I’m happy that they are taking these problems more seriously. It means we have to design the NPU and design the interfaces correctly, because it’s no longer the standard AXI interfaces, and it raises questions about how we reduce the latency of this bus,” Theivendran said. “On the chiplet side, it’s all UCIe-standard with a SerDes-like interface, which is very high frequency and all that. But a traditional AXI is not required anymore, so how do we plug in with that? That’s where our NPU now changes.”
Against that backdrop, the practical question becomes how design teams should adapt their design choices to work within these new constraints. For many, it means replacing fragmented handoffs with workflows built for cross-die design, packaging, and test.
“In a traditional monolithic design, if a localized defect occurs, you will discard a single die,” said Long Thanh (Kevin) Bui, AMS senior manager at Mixel, a Silvaco company. “In a chiplet architecture, one failed interconnect or a single defective I/O chiplet can ruin an incredibly expensive, fully assembled package. Thus, engineering teams need a unified workflow because the package is the system. They must coordinate complex multi-die interactions and mitigate failures before physical tape-out.
Structured workflows matter in a chiplet design for several reasons. “First, there is the complexity explosion,” Bui said. “Multi-die systems multiply failure points, from interconnects and thermal coupling to warpage. Manual or disconnected processes lead to missed interactions, rework, and escapes. Second is cross-domain coordination across architecture, packaging, test, reliability, and multi-vendor supply chains. Third is scalability and repeatability. Chiplet designs are built for reuse across products, so workflows enable modular, standardized processes instead of one-off efforts. Fourth is risk reduction. Early predictive modeling and in-design analysis catch issues before tape-out. Hierarchical testing and KGD help ensure only known-good components are assembled. Fifth is efficiency, because automated transitions between steps — modeling, analysis, and verification — reduce errors, speed iteration, and support collaboration.”
The focus, in other words, has shifted from on-chip design to cross-die behavior. “The boundary of concern has moved from inside the chip to the interface between chips. New standards like UCIe have pushed workflows beyond proprietary, closed systems into open ecosystems, where chiplets from different vendors must work together reliably. Advanced packaging — including 2.5D/3D, interposers, and hybrid bonding — also introduces new physics such as stress, thermal gradients, and variables like bump pitches and materials,” he said.
What a workflow means in chiplet design
In semiconductor engineering, a workflow is a repeatable, end-to-end sequence of engineering steps, tools, data, and decision gates designed to ensure reliability from concept through silicon and into the full product lifecycle.
Meanwhile, a chiplet workflow is a concurrent, co-design loop that continuously verifies the functional, electrical, and physical integrity of multiple distinct dies when packaged together as a single high-performance system. “For chiplets, a robust workflow is critical,” said Bui. “Unlike traditional monolithic SoCs, where reliability was largely confined to a single die, chiplet systems introduce a fundamentally new level of complexity: multiple dies, high-density interconnects, advanced packaging, plus system-level behavior. Reliability is no longer die-level-only. It has become a true system-level challenge spanning multiple domains and disciplines.”
Others agree. “When we talk about chiplet reliability, we focus on four core areas — thermal, mechanical, power integrity, and signal integrity,” said Lang Lin, principal product manager at Synopsys. “All four need to be evaluated before a chiplet design can be taped out with confidence. In practice, that means using a holistic EDA workflow that analyzes all four areas together. Engineers rely on multi-physics solvers to study how thermal, mechanical, power, and signal effects interact, because none of them can be treated as isolated problems anymore. Modern flows are both multi-physics and multi-scale, allowing teams to evaluate different physical effects across the system and identify the worst-case scenarios. For example, one chiplet might fail because cooling is insufficient and temperatures rise too high, while another might run into power integrity issues because it is too far from its power source.”
This is a difficult multi-physics problem. “We usually start from an initial state. The chip is at room temperature, the power supply is at its nominal voltage, the signals are running at the expected data rate, and the package has no significant stress or warpage,” Lin explained. “But once the chip begins operating, all of those conditions start to change at the same time. As the temperature rises, leakage power increases, which raises total power. Higher temperature also slows the chip because the delay increases. At the same time, heating can create mechanical issues such as thermal expansion mismatch and die warpage. None of these effects happens independently. They all interact simultaneously, which is why solving chiplet reliability becomes a complex engineering problem.”
For the chip architect, all of this requires a lot of co-working because there are multiple pieces involved. “There are the interface people, there are standards, there’s our side of IP design, and there’s the system-level testing,” Expedera’s Theivendran said. “So in terms of using the right parts and getting things working end-to-end, there are multiple pieces now. And there’s also the verification side. You would have to provide a UVM-based infrastructure test bench, drivers, monitors, etc., just to emulate what our environment looks like, because now we’re sort of a mini-chip in that chip. It’s not just a standard IP. It’s something more. It’s just like a chip. There are different constraints there.”
This is quite different from a traditional planar SoC workflow. “If we’re putting together a system, that workflow would include architecture, design, testing, system-level testing, module-level testing, and then working up — and eventually, netlist, gate-level testing, and power analysis,” Theivendran said. “There’s a lot more validation, but we can’t do the system-level testing. We can only do our block-level, IP-level testing. So it would look like the traditional workflow, but with a lot more steps and nuances that we need to worry about.”
What a chiplet workflow must include
Because stacked dies are so interdependent physically and electrically, a robust chiplet workflow must cover several distinct tasks, according to Mixel’s Bui. The core components of a chiplet workflow include:
Fig. 1: Example of an integrated thermal design and modeling flow. Source: Siemens EDA
Multi-physics co-design is non-negotiable. “Chiplet designs are inherently multi-physics problems,” said Nilesh Kamdar, general manager at Keysight EDA. “Heat rises between vertically stacked dies. Mechanical stress from drops or vibration affects solder connections and electrical performance. In data center applications, co-packaged optics introduce optical physics into a stack that already manages electrical and thermal interactions. None of these can be modeled in isolation. A material selected for electrical reasons may complicate heat management. Optimizing thermal performance may impact mechanical stability. The entire system has to be analyzed. Consider what happens when a smartphone overheats while trying to connect to a weak signal. The excess heat drains the battery faster, forcing the radio to work harder, which generates more heat. In a chiplet stack, this feedback loop occurs across multiple dies, materials, and physical domains simultaneously.”
Verification compounds the challenge. “Traditional block-level approaches were designed for single-die systems and do not account for the interactions across multiple dies, process nodes, and packaging layers,” Kamdar noted. “Effective validation requires a system-level perspective from the outset, testing each die individually before confirming that performance holds once the full stack is assembled. For example, thermal and crosstalk are invisible at the component level and only appear when the entire system is modeled. Hardware-assisted environments can catch timing and interoperability issues that static analysis misses, but only when simulation keeps pace with the design.”
There are additional considerations for simulation. “If you just want to build a simulation model, there is a bit of complexity to it,” Siemens EDA’s Vass-Vernai said. “You need to have a strong understanding of the tools, sometimes even meshing techniques, physics, and it’s sometimes a career that you pick up over the years. We were trying to democratize it, and if you look at those tools from just a pure simulation perspective for semiconductors, for example, the whole idea is that you would create something like a spreadsheet or an input field. You put in all the details of your package for a standard package style. Then the tool would build up a model, build it, mesh it, and configure it. We’ve been trying to bring down the barrier of entry for the simulations. When it comes to die stacking, you really want to do that because you want to make sure the electrical designers can make quick turnaround decisions. The problem is that this template, spreadsheet-based input, is not working anymore because the packages are not standard. It’s up to the technologies you’re working with, your engineering skills, your imagination, and the type of package architecture you’re building. We still need to bring the barrier for entry into simulation lower, but we can do it in a way we are used to.”
At the same time, this is driving efforts to develop digital twins for packages. As architects define the floorplan, chiplet placement, stacking, interposer materials, connections, and netlist, they are already generating much of the mechanical information needed for simulation. Instead of building separate simulation tools and relying on simulation engineers to recreate the model later, that electrical definition can be turned into a multi-physics model. It still requires setup, such as material properties, power assignments, and boundary conditions, but the goal is to make the process as simple and streamlined as possible. That way, electrical package designers can use their initial design to generate a thermal or thermo-mechanical version of the digital twin much earlier in the workflow.
How AI is reshaping the workflow
Adding AI into the chiplet workflow can have a significant impact, as well. “In predictive modeling and analysis, AI can improve thermal and mechanical simulation, anomaly detection in testing, and yield forecasting,” Mixel’s Bui said. “It processes massive multi-physics data sets to predict hotspots, warpage, and failure risks earlier and more accurately. In auto-routing, AI can help automate the complex routing of thousands of micro-bumps between chiplets while minimizing interference. In verification and debug, AI can accelerate regression, root-cause analysis, and hierarchical testing. It can also model interconnect behavior and help generate test patterns for KGD and inter-die links.”
Things are changing so fast with AI that even the lingo is evolving. “We don’t like to say scripts anymore,” Vass-Varnai noted. “We still do scripting, but now we talk about automation. When we talk about automation, instead of creating scripts, Google is creating AI agents on top of these tools and teaching those agents how to run the different tools and how to create the flows. That’s where we are heading. We have another plan to combine that with LLMs, because the best way to do this is to be able to prompt the tool in natural language, explain what type of package you’d like, from what components, and work with your assistant to help you figure out the design. That is clearly the direction we are heading. I know all our competition is already doing it. I don’t think anybody is there yet, but it’s a very tight race, and whoever does this the best can win.”
In fact, the whole EDA business is about workflow. “To run it, you need the design data, and with the design data, you run tools on it, generate more data, run more tools on that data, and then you want more tools on that data,” noted Dean Drako, CEO of IC Manage. “That’s your workflow. What is happening is the workflow is being enhanced with agentic AI, so what we’re doing is using agentic AI in the workflow to do IP lifecycle management. By using AI enhancements, the new capabilities make it faster and easier to reuse system components/IPs by replacing a lot of the manual stuff with workflows for packaging and support and discovery, so that the engineers can find it, figure out if it’s the right thing, and then, tweak it if necessary, or verify it using the AI that we’ve created for them.”
Further, AI agents can be used to run quick predictions based on many simulations. “There are companies out there doing that fully,” Vass-Varnai added. “We have tools internally that we are eyeing to add to our workflow. If you want to train AI, you need well-structured, clean data, and we are also offering data management, so we can make that happen. But even if you make it happen, it would be best if you could train that AI on many, many design rounds from multiple companies.”
Matt Commens, senior director of product management at Synopsys, agreed that AI will rapidly reshape chiplet reliability workflows. “A lot of the activity around how a design gets created and set up, and then how it gets run, is going to be through agents. Everybody wants their workflow automated, so we’ve engaged in some projects to build out hyper-automated workflows with certain customers for certain activities. Of course, we’re always enhancing our own workflows to do more integration, such as the multi-physics workflow. People want it very specific for their application. This activity is going to get taken over by AI pretty darn quick, and we’re seeing that already. Ansys – now Synopsys – consciously embarked on an API-first initiative four or five years ago, and this was before ChatGPT came out. The reason we were leading API-first was to build workflows. For one of these projects that we did with a customer to do very tight automation, we built an API that we call PyAEDT. It’s open-source, it’s on GitHub, and it’s documented. It’s really active, and all the language models know how to code in it because they were all trained on it.”
Still, Commens does not expect an overnight shift to fully AI-driven workflows. “This will be a gradual transition,” he said. “The design community cannot simply abandon its existing methods overnight. Teams are working within established tools, processes, and habits, and there are business constraints as well. As workflows become more automated and complex, AI usage will require increasing compute resources and energy. The industry will need to address whether enough data center capacity and power are available to support that demand. So while there are real limits today, the direction is clear.”
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