As the semiconductor ecosystem pivots to AI, it is transforming how IP is created, verified, managed, and sold.
Key Takeaways:
AI is becoming part of the everyday work of IP developers who build, verify, package, support, and sell reusable design blocks. It also is changing what the IP does, how it’s created, verified, and managed. And it is altering how it is found, licensed, reused, and supported over time.
AI is helping teams write and review RTL, generate tests and documentation, debug issues faster, organize metadata, and make IP easier for other engineers to find and adopt. Still, it does not remove the need for expert judgment based on deep engineering experience. Developers still need to understand the design intent, review what AI produces, close coverage in verification, and ensure the IP is sufficiently reliable for real silicon.
The biggest change is that IP development is moving from doing every task manually to guiding, validating, and improving AI-assisted flows across both the technical and commercial IP lifecycle. This is apparent in the explosion of customizable IP.
“The main reason for this is that the long pole for IP was the spec-to-RTL generation, tweaking it, and verification,” said Sathishkumar Balasubramanian, head of product for EDA AI & Solido at Siemens EDA. “What we are seeing is that, with all the AI innovations — especially in agentic AI — most of the innovation is happening in RTL code generation and in how they can speed up the debug and verification side of things. So we are seeing many more flavors of IP coming into play, which is really helping IP vendors customize IPs for different use cases without sacrificing resources or time.”
In the past, engineers took shortcuts by adding a software layer on top. But with AI, they can churn out better RTL faster, and then verify it on the front end.
“It’s trending toward being able to offer different flavors of IP with fewer resources and compute,” Balasubramanian said. “There’s a lot more advanced configuration happening at the IPs, and AI allows developers to easily change how they target each other and applications. That’s on the front end. AI is really helping on the back end, too. We are seeing a lot more chiplets right now, where we used to worry about not being able to mix-and-match different process nodes. The AI helps because the back end is much more complicated when you’re working on a chiplet and doing floor planning. How do you monetize that? How do you do your bump array for your IC? That’s where AI is helping them come up with a better configuration, develop a better back-end design, and create a better implementation all the way up to the packaging level. Think of this as an accelerator that helps you do things faster and better. It means that you can essentially do a lot more IPs. Also, you can use the same IP in different packaging based on chiplets so you can sell it to a lot more customers.”
That expansion in IP variety creates other problems — keeping every version current, discoverable, and ready for reuse. This is where AI begins to matter, not only as a design accelerator, but as a lifecycle management layer for IP.
AI is embedded in IP lifecycle management
AI is an enabler for how IP is managed, packaged, and discovered across its lifecycle, rather than a tool that simply bolts onto existing flows.
“We added a lot of AI, but now we’ve added AI specifically for this IP lifecycle management component,” said Dean Drako, CEO of IC Manage, pointing to AI-driven IP packaging. “It automatically keeps the IP packaging and everything up to date for the engineer.”
Before AI, this was a tedious and error‑prone manual process. “This is all about the lifecycle management portion of the system, since the goal is to keep IP consistently production‑ready as it moves through different projects and teams,” Drako said. “And with AI-driven IP discovery, it finds the IP [you] want and makes sure it has the right stuff.”.
Taken together, these capabilities position AI as an infrastructure layer for ongoing IP health, reuse, and discoverability within today’s chip designs.
Verification IP is becoming AI‑augmented
Verification was one of the earliest use cases for AI in IP. But while it may seem counterintuitive, verification IP is more deeply rooted than ever in the verification process. Varun Agrawal, director of product management at Synopsys, characterizes AI as a “second vendor” that runs parallel with VIP like a virtual verification partner. “Agentic AI can be a second parallel vendor that you work with to augment your verification, along with the main vendor that you’re working with,” he said.
The most visible impact today is in how teams translate specifications into meaningful tests. Given a dense protocol spec, AI can help interpret the document and automatically generate test scenarios and payloads that are tightly correlated to that spec. “The very first part I see is spec correlation,” Agrawal said. “If I have this spec, if I’m writing some test scenarios, maybe I can generate a test scenario automatically. How compliant is it? In terms of payload generation, agentic AI is helping a lot with verification. How can I get to a payload fast that is correlated to what I’m trying to verify?”
Other key questions are whether you can generate tests at all, and how quickly you can reach sufficient depth and coverage across the protocol’s behavior.
As chips become larger and more complex, another critical pain point is how to wire up the verification environment. Thousands of blocks, multiple VIPs, and complex interconnects make assembly a nontrivial engineering task. Here, Agrawal sees AI stepping into an orchestration role. “The second layer where I see AI helping tremendously is in terms of assembly. I now have 1,000 components on my chip. How do I assemble a verification infrastructure to cater to that? Orchestrating your verification infrastructure, that is where it is helping.”
Debug and coverage closure are other prime targets for AI. Modern verification produces an overwhelming volume of logs, traces, and coverage data. Eventually, in the form of multiple cooperating agents, AI can help with faster debugging, root cause analysis, and prioritizing what to look at next. “Where AI is helping is debug,” Agrawal said. “Coverage goals, root cause analysis, faster debug.”
So the VIP, testbench, and infrastructure don’t disappear, but AI helps IP development teams get more value out of what they already have.
Synopsys is applying these same ideas to its internal VIP development flow to read specs, propose test plans, and generate significant portions of code. Still, those outputs are reviewed and refined by senior domain experts.
“We’re also treating AI as a parallel vendor to us, where the AI looks at the spec, gives its point of view, gives out its test plan,” Agrawal said. “Then we have experts who have been in the industry for 20-plus years. They review it, they augment it. Then we go to the next part, where we generate code. Some parts of the code are being generated by AI. There again, the experts verify it and make sure there are the right milestones and KPIs to ensure a higher level of quality.”
The speed of AI is adding pressure to IP development teams
The rapid buildout of the edge adds more challenges. AI is moving so fast in some vertical markets that even the people building the underlying IP are struggling to keep up. In those domains, AI is actively reshaping how IP must be designed, tooled, and maintained over its lifetime.
Traditionally, vendors sold synthesizable IP based on performance, power, and area specs. Those still matter, but in an AI‑driven world, they’re no longer enough. It’s not just about raw compute. It’s about how quickly a new model can run well on shipping silicon.
“For customers, efficiency and speed of landing new models is critical,” said Steve Roddy, CMO at Quadric. “People are desperate to get the latest and greatest model and get it landed on the platform as soon as possible. When models change, and you know they’re going to change, how quickly can that new model land on the target? Can I do it myself as the OEM? Do I need to go to somebody else to get it ported?”
Hardened IP in the form of chiplets adds other challenges, particularly in 2.5D assemblies where chiplets are used to boost performance and provide more flexibility in a design. In those devices, signals need to travel longer distances than on a single SoC, tilting the focus toward power and performance versus area.
“Chiplets have to be scalable not just die-to-die, but chip-to-chip, and rack-to-rack,” said Purna Mohanty, CEO of SignatureIP. “We need to make sure that our baseline IPs are fine-tuned for scale in terms of bandwidth, latency, and power, and not just in terms of the number of devices. They need to be micro-architected from the ground up, and to balance between power, performance, and area.”
Microarchitectures can be daunting in chiplets. Interactions between those chiplets need to be carefully orchestrated. “It’s a three-dimensional problem,” Mohanty said. “The baseline design is RTL. The microarchitecture is RTL. But you also need to control the RTL, and you need a tool in place to control the configuration of that. So, the tools become very complex because of all the features that go into the RTL.”
AI helps speed this process up significantly. And as models grow and change, edge IP is being pulled into a cycle where better efficiency enables more demanding AI workloads, which in turn force the next generation of IP.
“As these applications are coming out, they require a lot more demand on compute,” said Amol Borkar, group director for Tensilica DSPs at Cadence. “But compute also means power. And then, it’s a vicious circle. We’re improving our processors to be more efficient, but that efficiency also opens the new requirements for new applications, which are also more demanding. You have to build new processors for that and just keep going around.”
Compilers and toolchains
That constant churn spreads the pain from the IP block outward to the full development environment around it. Because AI models change faster than silicon, compilers and toolchains become increasingly important for keeping IP usable, flexible, and competitive.
“Customers’ most important models are often the ones they won’t share,” said Jason Lawley, product marketing director for NPU accelerators and SDKs at Cadence. “From a customer point of view, there are two important models. The second most important model is the model that they can give us. But the first and most important model to them is the one they can’t share. It’s their secret sauce.”
This is where compilers can really help. “It becomes incredibly important for the software and the compilers to be able to take that network that we can’t see, that we don’t have access to, and compile it and lower it down so that it works optimally on whatever the hardware it’s going to run on,” Lawley said. “As you see these models evolving, compilers must keep up with the evolution of the networks and the operators. It’s incredibly challenging, incredibly important, and incredibly expensive.”
It’s also time-sensitive. Quadric’s Roddy noted that IP vendors can’t be the bottleneck for model updates. “No downstream OEM wants to be reliant upon the box builder or the chip builder or, heaven forbid, the IP licensor three levels removed to port a new model. The tooling has to be bulletproof. The automotive company with their data scientists has to be able to land their new updated algorithm with high performance. It has to run at speed easily without 12 layers of NDAs.”
Borkar underscored just how relentless this model churn has become. “The models are changing really fast — daily, hourly, even by the minute,” he said. “If you’re getting updates from Hugging Face, you’re probably getting emails every couple of hours that there’s a new variant of an SLM or a VLM, or a multimodal model.”
The downstream effect on IP teams is brutal. “These models are coming in every day. There is a new type of operator layer coming in,” Borkar said. “Having the whole compiler flow, having it be able to map to your hardware, is a lot easier said than done. Do you have some countermeasures to do some emulation for those operators or layers to run?”
One consequence of this churn is that no single fixed engine can handle everything. Most experts argue for more heterogeneous and programmable SoC subsystems, and a one-size-fits-all block won’t suffice. “If you look back a few years ago, there were DSPs, NPUs, GPUs, and GPGPUs,” Borkar said. “But it doesn’t look like one magic bullet can solve everything. We’ve got NPUs, but we’ve got DSPs, as well. And the challenge that we’re facing is that not everything in a design runs in one piece. You usually need to have some type of a heterogeneous subsystem — maybe an AI co-processor with an NPU plus a CPU — providing that level of flexibility for consuming the networks.”
On top of that, the numeric formats themselves are in flux. Siemens’ Balasubramanian described what he’s seeing from the model side. “With agentic AI, a lot of folks are playing with the floating-point precision to trade off accuracy and being able to handle a lot more with the given memory. There’s quite a bit of experimentation happening. The workload is increasing. There is much more orchestration, many more unknowns. Then, if the IP developer changes the floating-point precision in terms of model updates, is the IP flexible enough to handle that, or do they need to change something very basic, even swap out architecture?”
Where these various components are placed and used determines how aggressively models need to be updated. “How fast the model is changing is a function of where the NPU sits in the pipeline,” said Sharad Chole, chief scientist at Expedera. “Is it close to the sensor, or to the application? NPUs that are close to the sensors don’t necessarily change that often, but as applications evolve in data centers or academia, that will have to be supported across the entire software and hardware stack. What we see as challenging is not really supporting new models. It’s much harder to support new models with performance.”
Those technical pressures do not stop at architecture, tooling, or verification. As AI changes how IP is built, maintained, and deployed, it’s also forcing suppliers and customers to rethink how IP is packaged, licensed, and monetized.
IP business models are adapting under AI pressure
AI is also reshaping how IP is packaged and sold.
“When it comes to the economics of IP licensing, the first thing you look for is that customers would need to have a licensing fee that they would need to pay the IP vendors, and it really depends on what type of use case they have,” said Raj Uppala, senior director of marketing and partnerships at Rambus. “Think of it as a Netflix model, for example, where you have different tiers based on the number of devices you can stream on, or the number of people you can add to your account. Similarly for licensing, you would have a single-use license where you could use the IP on a monolithic chip, or a multi-use license for different projects and chips. And depending on your usage of different IPs, if you have many projects that you’re working on, customers can also look at a subscription-based model.”
At the same time, volume-driven royalty structures and chiplet-based design are reshaping traditional single‑use assumptions. “From the royalty perspective, imagine a customer who has not too high volume,” Uppala said. “In that case, they have an option to pay royalties based on volume. But imagine, on the other hand, if you have a ton of volume, and you’re selling millions of units of your solution. In that case, you have an option to make a royalty buyout payment upfront and not worry about the royalty later. Chiplets are a new discussion point emerging, and it does introduce some new challenges. For example, if a single-use IP was used on a monolithic IC in a chiplet model, you could take that same chip and use it in different modules or different SoCs. Now, that becomes a problem because, in effect, that is a multi-use, and some of these issues will need to be resolved as chiplets become more commonplace.”
These are important considerations, given that IP development is increasingly tied to workloads, platforms, subsystems, and long-term partnerships, not just one‑off core deliveries. But new commercial models also introduce new responsibilities. As IP becomes more reusable, AI-assisted, and deeply embedded across products and platforms, questions of ownership, control, security, and governance will become harder to separate from the IP itself.
Incorporating proprietary IP into foundation models also raises questions about the ownership of AI-generated code, necessitating contracts and technical safeguards. “People are interested in private agents largely because of privacy and control over their own data,” observed Ronan Naughton, director of AI product management at Arm. “That means security must extend across the entire software stack, not just the SoC. Arm has been designed with security at its core from the beginning, and as data moves from cloud to edge and back again, protecting that handoff will be critical. It is the responsibility of all manufacturers, OEMs, and partners to safeguard user data and privacy so AI agents can improve people’s lives without compromising security.”
This means IP providers must continuously strengthen security features in their chips. “When we talk about our chip evolution, right in every single generation of the chip, we are adding in security features to make it more secure. And it is absolutely intrinsic and essential in our chip architecture,” Naughton noted.
Human expertise around IP remains central
For all IP developers, AI‑aware data governance and security requirements are now first-class design constraints. Those risks make clear why AI cannot be treated as a fully autonomous substitute for IP judgment. Even as AI takes on more of the development workflow, experienced engineers remain essential for interpreting results, enforcing quality, and deciding what is ready for production silicon.
AI is powerful, but IP still depends on human experts. Currently, AI can mostly replace mediocre or repetitive tasks, but not deep IP or verification expertise.
“With agentic AI, we call it human on the loop,” Siemens’ Balasubramanian said. “One thing we figured out with GenAI was that the biggest bottleneck was the human in the loop. We became the bottleneck, so we replaced certain very basic tasks that could be automated, allowing humans to be more of an orchestrator. But humans are always there.”
The still unanswered question is which humans. “A lot of what I find AI doing is replacing the mediocre,” Nandan Nayampally, chief commercial officer at Baya Systems, noted. “They don’t know what they’re doing with it. But you’re not going to change the specialists.”
That makes the most realistic path forward less about replacing IP developers and more about changing how they work with AI. The strongest gains will come when AI accelerates routine analysis and generation while engineers provide context, judgment, and accountability.
“AI is going to make our human developers significantly faster and better,” said Cadence’s Lawley. “It’s going to be a collaboration of this information that gets put with the human part of the creativity, plus maybe a little bit of creativity from the AI model. But it’s going to be that collaboration that’s going to make the big difference.”
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