Chip Industry Week In Review

By The SE Staff - 17 Jul, 2026 - Comments: 0

Advanced manufacturing, packaging Intel Foundry will invest €5B to expand Intel 3 capacity at its Leixlip, Ireland campus. The company also entered high-volume manufacturing for a subset of Panther Lake processors manufactured on its 18A using ASML’s High-NA EUV technology. UMC delivered the first production wafers for SILITH’s 1.6T silicon photonics platform from its 300mm Singa... » read more

AI Models On The Edge

By Ed Sperling - 14 Jul, 2026 - Comments: 0

Moving from large language models in the cloud to small language models at the edge is much more complicated than just slimming down the algorithms. It requires changes in both hardware and software, and the constraints can vary greatly from one market segment to another. Daniel Firu, CPO and co-founder of Quadric, and Ravi Chakaravarthy, vice president of software at the company, talk about ho... » read more

AI Is Rewriting The IP Playbook

By Ann Mutschler - 09 Jul, 2026 - Comments: 0

Key Takeaways: AI is reshaping the entire IP lifecycle, from creation and verification to discovery, licensing, and support. Fast-changing AI models are making flexible IP, robust toolchains, and faster deployment essential. Human expertise remains critical for reviewing, validating, and governing AI-assisted IP development. AI is becoming part of the everyday work o... » read more

Benchmarking An NPU At Scale

By Marc Meszaros - 09 Jul, 2026 - Comments: 0

With every Chimera SDK release, something quietly industrial happens: the entire 300+ model zoo gets automatically recompiled and re-profiled across a broad sweep of hardware configurations and the results land in DevStudio in the process. No one is hand-typing FPS numbers into a slide or running a single model on a single configuration to cherry-pick for a datasheet. The whole zoo moves forwar... » read more

Agentic AI Is Changing Data Center Architectures

By Ann Mutschler - 11 Jun, 2026 - Comments: 0

Key Takeaways: The rise of agentic AI is shifting data centers from GPU-centric number crunching to CPU-driven orchestration, where managing long-running reasoning loops and context is just as important as raw compute. Integrating CPUs, GPUs, and stacked memory into tightly coupled multi-die architectures with varying workloads makes it much harder to ensure they will be reliable and ef... » read more

Vision-Language-Action Models Arrive

By Mike Leonard - 14 May, 2026 - Comments: 0

The AI model type capturing the most attention across robotics and autonomous vehicles right now is the vision-language-action model, or VLA. At embedded AI conferences this year, particularly the recently held Embedded Vision Summit, VLAs were a main topic of discussion – not as a research curiosity, but as the architecture that teams building autonomous systems are actively targeting. If yo... » read more

Designing Chips In The Context Of Rapidly Evolving AI

By Ann Mutschler - 04 May, 2026 - Comments: 0

Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

Can Edge AI Keep Up?

By Ann Mutschler - 23 Apr, 2026 - Comments: 0

Key Takeaways: Model development is outpacing silicon design cycles, so edge AI architectures must prioritize adaptability. The required cadence for model updates is highly application-dependent and is closely tied to product lifetime and operational risk. Adaptability can conflict with power, performance, and area targets, so effective heterogeneous architectures and robust softwa... » read more

Chip Industry Week In Review

By The SE Staff - 17 Apr, 2026 - Comments: 0

Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

Heterogeneous NPU Data Movement: What The Execution Flow Shows

By Steve Roddy - 14 Apr, 2026 - Comments: 0

Heterogeneous NPU designs bring together multiple specialized compute engines to support the range of operators required by modern AI models. This approach enables coverage across diverse workloads, but it also introduces a structural consequence: intermediate data must move between those engines. That movement consumes power, adds latency, and requires additional silicon resources, with effect... » read more

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tag: Quadric

Chip Industry Week In Review

AI Models On The Edge

AI Is Rewriting The IP Playbook

Benchmarking An NPU At Scale

Agentic AI Is Changing Data Center Architectures

Vision-Language-Action Models Arrive

Designing Chips In The Context Of Rapidly Evolving AI

Can Edge AI Keep Up?

Chip Industry Week In Review

Heterogeneous NPU Data Movement: What The Execution Flow Shows

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