tag: Quadric

Startup Funding: Q1 2026
By Jesse Allen - 13 Apr, 2026 - Comments: 0

The new year started off with a bang for private semiconductor companies, with 18 garnering mega funding rounds exceeding $100 million, and two, Rapidus and Cerebras, reaching the $1 billion mark. Predictably, the vast majority of those are either designing chips primarily for AI inference workloads or attempting to overcome bandwidth limitations by improving interconnects from the chip level t... » read more

A New Era For Co-Processing
By Brian Bailey - 09 Apr, 2026 - Comments: 0

Key Takeaways: There is no single processor capable of executing everything efficiently, meaning that multiple processors are required. Maximum efficiency is gained by minimizing the movement of data. Architects must maximize efficiency for today's workloads, while also adding enough flexibility to handle tomorrow's. New processor architectures are rapidly evolving thanks to... » read more

Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
By Ann Mutschler - 09 Apr, 2026 - Comments: 0

Key Takeaways: Edge AI performance is about low latency and power efficiency, not peak TOPS. Memory bandwidth and data movement now limit edge AI more than compute. Successful edge AI requires balanced hardware, software, and fast model updates. Experts At The Table: Today’s chip architect must contend with multiple factors when architecting AI processors for fast and effi... » read more

State Of The Market For Edge Silicon
By Ed Sperling - 08 Apr, 2026 - Comments: 0

The explosion of data and the rapid ramp of AI is causing significant changes in how chips are architected. At the edge, the key metrics are power, latency, and performance, but those can vary significantly by application and by workload. Steve Roddy, chief marketing officer at Quadric, talks about the need to balance performance and efficiency with flexibility for different applications, what ... » read more

Memory Wall Gets Higher
By Brian Bailey - 26 Mar, 2026 - Comments: 1

Key Takeaways An increasing percentage of the chip area is consumed by the same amount of SRAM for each node shrink. The problem is not limited to leading-edge AI, as it will eventually impact even small MCUs and MPUs. Architectural changes may be required. Stacking SRAM chiplets on logic is possible but expensive. SRAM is a vital piece of all computing systems, but its fail... » read more

Chip Industry Week in Review
By The SE Staff - 20 Feb, 2026 - Comments: 0

The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

The On-Device LLM Revolution
By Steve Roddy - 20 Feb, 2026 - Comments: 0

The AI world is experiencing a fundamental shift. After years of cloud-centric inference dominated by massive data center GPUs, we're witnessing an accelerating migration of language models to edge devices. These are not the trillion-parameter behemoths that require server farms, but the "Goldilocks zone" models: 3B to 30B parameters — large enough to deliver genuinely useful AI capabilities,... » read more

The Race Begins For Much Bigger Abstractions In Data Centers
By Ed Sperling - 17 Feb, 2026 - Comments: 0

Key Takeaways Data center build-out is enabling much larger and more complex abstractions. Competition is building for digital/virtual twins across multiple industry segments, including automotive, aerospace, and chip manufacturing. AI, and particularly AI agents, will play a significant role in sorting through data to find potential trouble spots. The frenzy of new data cen... » read more

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
By Ann Mutschler - 12 Feb, 2026 - Comments: 1

Key Takeaways • Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems. • As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system. • Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by... » read more

Changes In Chip Architectures At The Edge
By Ed Sperling - 04 Feb, 2026 - Comments: 0

Edge computing is all about low latency, within a tight power budget, and with sufficient performance. This is very different from an AI data center, where the real focus is on data throughput between processor and memory. Achieving those goals requires a focus on what different processing elements bring to the table. Nigel Drego, co-founder and CTO of Quadric, talks about how these different c... » read more

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