Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 1

By Archana Cheruliyil - 26 Nov, 2024 - Comments: 1

This is the first of a three-part series on HBM4 and gives an overview of the HBM standard. Part 2 will provide insights on HBM implementation challenges, and part 3 will introduce the concept of a custom HBM implementation. Relentless growth in data consumption Recent advances in deep learning have had a transformative effect on artificial intelligence (AI) and the ever-increasing volume of ... » read more

Extending The DDR5 Roadmap With MRDIMM

By Zaman Mollah - 14 Nov, 2024 - Comments: 0

Given the voracious memory bandwidth and capacity demands of Gen AI and other advanced workloads, we’ve seen a rapid progression through the generations of DDR5 memory. Multiplexed Registered DIMMs (MRDIMMs) offer a new memory module architecture capable of extending the DDR5 roadmap and expanding the capabilities of server main memory. MRDIMM reuses the lion’s share of existing DDR5 infras... » read more

Distributed Shared Memory That Enlarges Effective Memory Capacity Through Intelligent Tiered DRAM and Storage Management (IIT)

By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "MegaMmap: Blurring the Boundary Between Memory and Storage for Data-Intensive Workloads" was published by researchers at Illinois Institute of Technology. "In this work, we propose MegaMmap: a software distributed shared memory (DSM) that enlarges effective memory capacity through intelligent tiered DRAM and storage management. MegaMmap provides workload-aware d... » read more

CXL-Based Heterogeneous Systems: How to Optimize and Future Directions (UCSD, Samsung, SK Hynix)

By Technical Paper Link - 06 Nov, 2024 - Comments: 0

A new technical paper titled "The Hitchhiker’s Guide to Programming and Optimizing CXL-Based Heterogeneous Systems" was published by researchers at UC San Diego, Samsung, SK hynix. Abstract "We present a thorough analysis of the use of CXL-based heterogeneous systems. We built a cluster of server systems that combines different vendor's CPUs and various types of CXL devices. We further ... » read more

GDDR7 Memory Supercharges AI Inference

By Tim Messegee - 17 Oct, 2024 - Comments: 0

GDDR7 is the state-of-the-art graphics memory solution with a performance roadmap of up to 48 Gigatransfers per second (GT/s) and memory throughput of 192 GB/s per GDDR7 memory device. The next generation of GPUs and accelerators for AI inference will use GDDR7 memory to provide the memory bandwidth needed for these demanding workloads. AI is two applications: training and inference. With tr... » read more

Improving The Gate Oxide Reliability in Gate First HKMG DRAM Structures (Sungkyunkwan Univ., Samsung)

By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Novel STI Technology for Enhancing Reliability of High-k/Metal Gate DRAM" was published by researchers at Sungkyunkwan University and Samsung Electronics. Abstract: "The challenges associated with semiconductor are increasing because of the rapid changes in the semiconductor market and the extreme scaling of semiconductors, with some processes reaching their te... » read more

Rowhammer Protection By Addressing Root Cause (Georgia Tech)

By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new technical paper titled "Preventing Rowhammer Exploits via Low-Cost Domain-Aware Memory Allocation" was published by researchers at Georgia Tech. Abstract "Rowhammer is a hardware security vulnerability at the heart of every system with modern DRAM-based memory. Despite its discovery a decade ago, comprehensive defenses remain elusive, while the probability of successful attacks grows ... » read more

Preparing For Ferroelectric Devices

By Katherine Derbyshire - 02 Oct, 2024 - Comments: 0

The discovery of ferroelectricity in materials that are compatible with integrated circuit manufacturing has sparked a wave of interest in ferroelectric devices. Ferroelectrics are materials with a permanent polarization, the direction of which can be switched by an applied field. This polarization can be used to raise or lower the threshold voltage of a transistor, as in FeFETs, or it can c... » read more

Enabling Innovative Multi-Vendor Chiplet-Based Designs

By Elad Alon - 26 Sep, 2024 - Comments: 0

Chiplets have emerged as a critical implementation paradigm for semiconductor products, primarily because they can deliver cost benefits relative to a non-chiplet-based approach. The first, most well-proven, and obvious benefit of a chiplet-based approach is manufacturing cost. Manufacturing cost benefits are accrued either from the appropriate selection of chiplet die size, or by optimizin... » read more

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)

By Shyam Sharma - 26 Sep, 2024 - Comments: 0

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: DRAM