Exploring Process Scenarios To Improve DRAM Device Performance


In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development


Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

Memory On Logic: The Good And Bad


The chip industry is progressing rapidly toward 3D-ICs, but a simpler step has been shown to provide gains equivalent to a whole node advancement — extracting distributed memories and placing them on top of logic. Memory on logic significantly reduces the distance between logic and directly associated memory. This can increase performance by 22% and reduce power by 36%, according to one re... » read more

LPDDR5X Opening New Markets For Low-Power DRAMs


Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market. This blog post talks about the evolutions of LPDDR DRAMs leading to the latest published standard of LPDDR5/5X. We also look at some of the traditional markets for LPDDR devices and how LPDDR5X is opening new specialized markets for the LPDDR DRAMs. History of LPDDR devices The first LPDDR standard,... » read more

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control


High-performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies. An effective prefetching mechanism can improve cache hit rate significantly. Data prefetching boosts the execution performance by fetching data before it is needed. While prefetching improves performance substantially on many programs, it can significantly red... » read more

Using Palladium To Address Contact Issues Of Buried Oxide Thin Film Transistors


A new technical paper titled "Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway" was published by researchers at Tokyo Institute of Technology and National Institute for Materials Science (NIMS). Abstract "Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures... » read more

Non-Destructive Metrology Techniques For Measuring Hole Profile In DRAM Storage Node


DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot... » read more

Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)


A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

Cache Coherency In Heterogeneous Systems


Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst... » read more

DRAM Cache for GPUs With SCM And High Bandwidth


A new technical paper titled "Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory" was published by researchers at POSTECH and Songsil University. Abstract "We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction o... » read more

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