Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.
Key Takeaways
Backside power delivery networks deliver power directly to leading-edge transistors from below the wafer, an architectural change that speeds processor performance, slashes power losses, and boosts power efficiency. But a BPDN also calls for many new manufacturing strategies to remove most of the silicon wafer, precisely align nanoTSVs with transistor source/drains, and new modeling efforts to reduce the thermal penalty associated with confining hot transistors between the frontside and backside interconnect stacks.
Still, leading IC manufacturers are making significant progress, especially given the near-simultaneous transition to nanosheet FETs from finFETs. Intel recently moved its 18A process with RibbonFET transistors and PowerVia into production. Samsung, an early leader that adopted gate-all-around (GAA) transistors at its 3nm node in 2022, plans to introduce backside power at its 2nm node (SF2). TSMC stated it will debut GAA at its 2nm node (N2), followed by its Super Power Rail at the 16Å node (A16).
Fig. 1: SEM image shows details of the PowerVia backside power connection. Source: Intel
Backside power delivery networks (BSPDN) reposition the power grid on the wafer backside so it doesn’t compete for footprint with the signals on the frontside. This fixes multiple problems that built up over generations of logic devices, most notably the high IR drop (voltage droop) that limits performance and power efficiency. This translates to high power losses associated with bringing power down from the top back-end metal levels, through 15 or more metal layers and high-resistive vias, before reaching the transistor contact level.
Backside PDNs reduces voltage drop by up to 30%, improving power integrity. And because the signals and power are segregated, backside power enables a looser metal pitch on the frontside interconnects, reducing lithography costs.
The benefits don’t stop there. “Backside power delivery naturally complements the vertical nature of gate-all-around devices, providing a more direct and much less resistive path to the transistor source compared to frontside via stacks,” said Andrew Appleby, principal product manager for logic library IP at Synopsys. “By removing power routing from the frontside metal stack, more routing resources are available for signals, with a reported 5% to 10% improvement in cell density for embedded memories.”
Implementing backside power further reduces the burden on lithography and etching processes. “Since the cost of interconnect layers generally scales up as pitches scale down, less aggressive scaling for the same number of signal wires means less cost per signal wire,” said Kevin Fischer, vice president and director of Interconnect and Memory Technology and Integration at Intel. “Intel 18A, for example, leveraged this to lower costs with single and direct patterning of lower metal layers, reducing mask count and step count by more than 40%.”
Core issues for backside power
Backside power delivery is vital for workloads that demand high power and rapid changes in power consumption, such as AI accelerators, gaming chips, and graphics processors.
“The biggest advantages are (1) being able to take advantage of relaxed-pitch metal wiring on the backside for power delivery, which reduces the IR drop, and is not limited to tighter-pitch wiring on the front side, and (2) by removing power delivery resources from the front side, we open up additional routing resources on the front side, improving routability and area utilization,” explained Dan Dechene, director of technology readiness & digital transformation at IBM Research.
The performance improvements are substantial. “A backside power delivery network enables a 20% to 30% reduction in IR drop, a 2% to 6% increase in maximum frequency, a 5% to 15% reduction in core area, and utilizations in excess of 90%, according to published reports, which is consistent with IBM’s internal benchmarking,” said Dechene.
But along with these massive benefits come new fabrication challenges. At scale, a BSPDN scheme must achieve excellent alignment between the backside metal and frontside transistor dimensions. Because backside processing occurs after severe substrate thinning, which induces warpage, tight overlay control requires transparent alignment marks and possibly landing pads to implement.
The jury is still out as to how dramatically backside power will impact heat removal from hot chips, particularly those with uninterrupted workloads like GPUs. What industry experts do know is that the thermal conditions are worse with backside power delivery.
“Thermal hotspots will likely get smaller and hotter and require designer attention,” said James Myers, program director at imec. “The precise impact will depend on design context, but according to our high-resolution thermal simulations of a cloud CPU SoC, the local thermal penalty arising from BSPDN can be as high as 14°C. There is a potential for DTCO level mitigations, such as maximizing metal density in the BSPDN to provide local spreading effects, or increasing via density in frontside BEOL to reduce thermal resistance to the cooler.”
Key steps — thinning, bonding, alignment
Backside power approaches allow the different metal layers to be optimally fabricated, with wider lines for power and ground on the backside, and thinner lines primarily for signals on the frontside. When they all shared the frontside, more expensive lithography steps were required for the early interconnects.
Though at least three different process integration flows are possible, we’ll walk through the Intel flow (see figure 2), since that will be the first to market.
Fig. 2: The transistors and power vias are fabricated first (a), followed by multi-level frontside metallization and dielectric seal (b), bonding to silicon carrier (c), then backside power processing. Source: Intel
The PowerVia flow forms the PowerVias early on, alongside n and p transistors. These vias can be copper-based or made from a lower-resistance metal, such as ruthenium. Next, the back-end-of-line (BEOL) metal stack is built up, followed by deposition of a protective hermetic layer. The wafer is then inverted and bonded to a carrier wafer, which is optimized for thermal conductivity to help heat removal.
With the support of the carrier silicon, the device wafer is then thinned down dramatically from its original thickness of >700µm to 1 to 3µm using wafer grinding, then finely planarized using CMP and perhaps dry etching. Now the wafer is ready for backside interconnect processing with two or more metallization layers.
Meyers outlined the biggest challenges with BSPDNs. “The first challenge is removal of the silicon substrate almost entirely to access the devices from the wafer backside. This requires bonding of the processed wafer to a different carrier wafer on the frontside to grind or polish down the wafer backside. The grinding and polishing need to be uniform across the wafer to ensure a flat starting surface for subsequent lithography and other processing steps. The second challenge is to align the backside metal layers to the source and drain contacts of the transistors on the front side without shorting to the channel or gate region in the middle. This requires tight overlay control of lithography on the wafer backside. The third challenge is to ensure a low resistance contact to the source-drain from the wafer backside with a thermal budget constraint, since there are copper layers on the wafer frontside.”
The choice of bonding material is critical as it enables more effective heat removal from the stack. “The dielectric used for bonding adds to the thermal resistance for evacuating heat, so the material needs to be carefully chosen,” said Myers. For this reason, companies are evaluating aluminum nitride (AlN) and other films for permanent fusion bonding.
Wafer back-grinding and CMP steps must deliver exceptional cross-wafer uniformity as the silicon wafer is ground from 775µm to tens of microns. This aggressive process distorts the wafer so severely that metrology and then lithography must compensate on a die-by-die basis. Foundries are building in metal alignment marks to identify precise transistor positions. Silicon is semi-transparent to infrared light, so IR light on the lithography scanner can illuminate metallic alignment marks. Nonetheless, the die-by-die compensation can be a time-consuming process in high-volume production. Overlay budget with a process, such as that shown above, is ̴10nm.
New strategies must be combined to meet such aggressive specifications. “Wafer thinning and mechanical risk have been managed with advanced grind/CMP/plasma thinning, temporary carriers, and strict bow/warp and TTV [total thickness variability] control,” said Fischer. “Back-to-front alignment and registration have been improved using two‑sided alignment, dedicated frontside alignment marks, engineered etch‑stops, and via‑middle style integration tuned to the device/MOL stack.”
In addition, the device wafer absorbs the stresses from wafer bonding and severe wafer thinning. “The bonding and subsequent backside wafer thinning create stress and wafer warpage, which are especially pronounced at the wafer edges,” Myers said. “This deformation makes it challenging to achieve a tight, uniform overlay of backside vias and metals on frontside features.”
All this must happen while ensuring the performance of 2nm transistors. “GAA nanosheet transistors and BPDN have to be co‑designed because the GAA device stack directly defines the ‘landing targets’ and process window for backside power vias,” said Fischer. “Leakage and isolation are handled with backside dielectric liners, deep trench isolation, and optimized well/STI and doping schemes. Low‑resistance, reliable power rails and vias are enabled through tailored barrier/liner and metal fill processes, EM‑aware design rules, and tuned thermal treatments. Defectivity and yield are improved through staged deployment (e.g., proving on a prior node), intensive in‑line inspection, and DTCO‑driven layouts that are more tolerant to variation.”
Beyond these key manufacturing issues, the backside PDN alters the design flow in important ways.
Design impact of backside power delivery
One of the results of adding a power grid to the wafer backside is greatly reduced congestion on the frontside. “From a place-and-route standpoint, routing congestion has become a key problem at advanced nodes. While shrinking transistor geometries allow us to pack more gates (and functionality) into a given square millimeter, connecting them with signal routes is more difficult and often leads to route congestion,” said Jim Schultz, principal product manager for digital implementation at Synopsys. “Separating power and signal routing reduces congestion, shortens signal paths, and lowers parasitic resistance and capacitance. This benefits high-speed IP blocks such as SRAMs and register files.”
As indicated, implementing backside power delivery mostly impacts place-and-route. “We have modified industry-standard place and route flows to be able to simulate BSPDN for several architectures,” said IBM’s Dechene. “One example is to skip the power routing step during the floor-planning stage. Another is to restrict the power routing to pre-defined backside levels.”
Modeling plays a key role here. “Thermal and stress effects from the added backside stack are modeled and optimized via co‑simulation and material/stack choices, while defectivity and yield are improved through staged deployment (e.g., proving on a prior node), intensive in‑line inspection, and DTCO‑driven layouts that are more tolerant to variation,” Fischer said.”
How and when backside power is implemented relies on critical risk management. “Going into the backside power scheme, Intel expected BSPDN architectures to be more costly and more complex. “However, for HPC applications, we expect the performance entitlement to outweigh the process and cost risks,” said IBM’s Dechene.
In addition, even though the backside PDN was originally conceived as a passive electrical structure, there are significant advantages to adding functionality to the wafer backside. “Clock tree networks tend to be the most critical routing networks on the chip. They are typically routed on the lowest resistance layers to provide low-latency clock signals. Backside metal can also be used for these critical clocks,” says Schultz, noting that because EDA tools no longer need to address congestion issues, less time will be spent in place and route.
One downside of moving the power grid to the wafer backside is coupling noise that can affect sensitive signals on the frontside. When power and signal lines are shared, the power lines intrinsically shield the signal lines. “Shielding of sensitive signals becomes more challenging without nearby power/ground,” said imec’s Myers. “But there is scope to move some long-distance signals, such as clocks, onto the backside where they are better isolated from aggressors on the frontside.”
Designers also take measures to compensate for hot spots on wafers, a condition that becomes worse with backside PDNs.
Thermal analysis
The transistors are now surrounded by FEOL interconnect stack on the frontside and power delivery stack on the backside, forming a sandwich around hot devices. Simulation work out of imec indicated that backside PDN approaches reach a peak temperature 14°C above that of traditional frontside PDN. [2]
The silicon substrate itself is a pretty good dissipator of heat for a non-metal [Si thermal conductivity = 140 W/(mK) vs. SiO2 = 1.4 W/(mK)], but because the substrate is largely removed in the backside thinning process, heat spreading is severely compromised. “The thermal penalty is mainly caused by the thickness reduction or even removal of the silicon substrate, resulting in reduced lateral thermal spreading, and the presence of the silicon carrier and bonding interface in the main thermal path towards the cooling solution,” said Herman Oprins, principal member of technical staff and R&D team leader of thermal modeling and characterization at imec.
“The thermal integrity of BSPDN is compromised due to a significant increase in thermal resistance between the chip cooling system and the active device layer,” reported Chun-Che Cheng of National Yang Ming Chiao Tung University. [3] “This increase in thermal resistance primarily arises from the high thermal resistance of the BEOL layer, an additional mixed bonding layer introduced during the wafer backside process, and the wafer thinning effect inherent in BSPDN technology.”
Cheng and colleagues demonstrated that the BSPDN structure results in higher chip temperatures than FSPDN, particularly at the package level, where heat dissipation faces greater obstacles. Thinning the substrate below 300nm results in elevated self-heating. In conventional flip-chip packaging, the heat path for FSPDN runs from the transistors through the bulk silicon wafer and through the thermal interface material to the heat sink. Some heat also escapes downward from the BEOL stack to the silicon interposer and out to the printed circuit board. Cheng and colleagues simulated a maximum temperature of 57°C with FSPDN.
In the case of backside PDN, the orientation of the chip is flipped so that heat dissipating toward the topside encounters resistance from the bonding layer to the TIM and heat sink. The upward path handles the bulk of the heat. The downward dissipation path goes through the backside interconnects, then the silicon interposer and PCB. Simulations by the University indicated a higher maximum temperature with BSPDN of 80°C.
The industry widely uses finite element modeling (FEM) simulations to predict the thermal performance of electronics packages at various stages, including chip design, floor planning, and package and heat sink design. Although simple average properties often proved effective for monolithic chip packaging with frontside PDN, more accurate models are now needed for backside PDN and 3D packages.
To simplify what amounts to a complex thermal simulation, IBM developed a machine-learning-based model that rapidly predicts the thermal resistance of BEOL stacks spanning several orders of magnitude difference in length scale using just the BEOL layout design, metal heights, and materials properties. [4] “Heat generated by transistors in the bottom chip of the 3D stack needs to travel across the BEOL layers of all chips bonded on top of it, as well as the chip-to-chip bonding layers,” said Prabudhya Chowdhury, a former IBM hardware engineer [currently at Microsoft]. The team added that the increase in transistor and power densities with each technology node will further exacerbate thermal management.
Based on a convolutional neural network, the ML model ties the design to local power densities, workloads, and material properties. This approach uses a dataset of FEM simulations over various BEOL layouts in an automated method that trains (80%) and then validates the results (20%). The model predicts thermal resistance in 1 x 1µm or 3 x 3µm segments, which is imported to a FEM solver for use in chip- and package-level simulations. The model produced accurate resistance predictions in a fraction of the time required by traditional models.
Next step is direct connect
There are different versions of backside power implementation. The next step that companies are researching and developing is called direct connect, where the nanoTSVs make direct electrical contact with the transistor sources and drains. All the tolerances become tighter with this approach, although it also provides the greatest benefits in frequency boost of processors, density improvements, and/or greater power efficiency. One significant challenge will be meeting an overlay tolerance of only 3nm for direct connect schemes.
Conclusion
The introduction of backside power delivery networks at the 2nm node is a major breakthrough because it addresses longstanding voltage losses that were significantly impacting HPC performance and energy efficiency. It relieves routing congestion that formerly consumed many engineering hours during a complex place-and-route program.
But backside PDN also requires new capabilities in the fab, such as wafer grinding, CMP and etching tools to remove most of the silicon, as well as wafer bonding processes, which must meet extremely tight specifications for wafer flatness and uniformity across 300mm wafers. Companies are developing more thermally conductive materials to replace traditional silicon dioxide for fusion wafer bonding.
The most difficult feats involve aligning the backside interconnects with frontside vias, preventing over-polishing that impacts parasitic effects and yield, and understanding the thermal impact so that designers can address hot spots in the context of this new thermal dissipation path. Backside PDN will present further integration challenges when CFETs replace nanosheet gate-all-around transistors. And, in light of what’s happening in backside power delivery and 3D, it seems clear that the industry requires innovative new methods for cooling, perhaps running coolant within layers of the chip itself.
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Excellent description for the lay engineer, thanks