TSV Complexity Leads To Manufacturing Bottleneck

By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

By Laura Peters - 23 Feb, 2026 - Comments: 1

Key Takeaways Backside power delivery reduces routing congestion at the most advanced nodes and offers significant performance improvement options. But it also adds a bunch of new challenges involving via alignment and interconnects. Still, leading-edge foundries are making progress, and all of them plan to offer BPDNs at 2nm and below. Backside power delivery networks deliv... » read more

CNT Nano Sandpaper For Atomic-Level Polishing (KAIST)

By Technical Paper Link - 15 Feb, 2026 - Comments: 0

KAIST researchers published "Carbon nanotube sandpaper for atomic-precision surface finishing." Abstract "Sandpapers, also known as coated abrasives, have served as the most familiar surface finishing tools since their first invention in the 13th century. However, they remain unsuitable for advanced industries requiring nanometer-level precision due to limitations in abrasive uniformity a... » read more

Manufacturing At The Limits

By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Transferable Hybrid Bonding Technique That Allows For High Integration Density In Advanced Packaging

By Brewer Science - 21 Aug, 2025 - Comments: 0

A technical paper titled "Hierarchical Multi-Layer and Stacking Vias with Novel Structure by Transferrable Cu/Polymer Hybrid Bonding for High Speed Digital Applications" was published by researchers at Industrial Technology Research Institute (ITRI) and Brewer Science. The paper demonstrates a "novel structure with hierarchical multi-layer stacking vias as well as transferred hybrid bonding,... » read more

Hybrid Bonding Makes Strides Toward Manufacturability

By Laura Peters - 28 Oct, 2024 - Comments: 0

Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical and reliability results. Advantages include interconnect scaling to submicron pitches, high bandwidth, enhanced power efficiency, and better scaling relative to solder ball connections. But whil... » read more

Optimizing Wafer Edge Processes For Chip Stacking

By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Defect Challenges Grow At The Wafer Edge

By Laura Peters - 10 Sep, 2024 - Comments: 0

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

CMP Process Characterization Using White Light Interferometry

By Bruker - 10 Sep, 2024 - Comments: 0

Faster computer and electronic processors require smaller features for integrated circuits (IC), which in turn require smaller and smoother substrate surfaces. Chemical mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it offers a superior means of removing unwanted topography in interlevel dielectric layers and achieving sufficient pl... » read more

Precise Control Needed For Copper Plating And CMP

By Anne Meixner - 20 Jun, 2024 - Comments: 0

Chipmakers are relying on machine learning for electroplating and wafer cleaning at leading-edge process nodes, augmenting traditional fault detection/classification and statistical process control in order to extend the usefulness of copper interconnects. Copper is well understood and easy to work with, but it is running out of steam. At 5nm and below, copper plating tools are struggling to... » read more

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