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Hybrid Bonding Basics: What Is Hybrid Bonding?


Hybrid bonding is the key to paving an innovative future in advanced packaging. Hybrid bonding provides a solution that enables higher bandwidth and increased power and signal integrity. As the industry is looking to enhance the performance of final devices through scaling system-level interconnections, hybrid bonding provides the most promising solution with the ability to integrate several di... » read more

How Quickly Can SiC Ramp?


Device makers across the globe are ramping silicon carbide (SiC) manufacturing, with growth set to really take off starting in 2024. It’s been almost five years since Tesla and STMicroelectronics threw down the gauntlet with SiC in the Model 3. Now, no one doubts the market pull for electric vehicles, but consumers are still clamoring for better range and faster charging. SiC devices are a... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Next-Gen 3D Chip/Packaging Race Begins


The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

The Effect Of Pattern Loading On BEOL Yield And Reliability During Chemical Mechanical Planarization


Chemical mechanical planarization (CMP) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different re... » read more

What’s Next For Transistors And Chiplets


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Angstrom-Level Measurements With AFMs


Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Reducing Rework In CMP: An Enhanced Machine Learning-Based Hybrid Metrology Approach


By Vamsi Velidandla, John Hauck, Zhuo Chen, Joshua Frederick, and Zhihui Jiao The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging


Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Characterization Of CMP Processes With White Light Interferometry


Faster computer and electronic processors require smaller features for integrated circuits (IC), which in turn require smaller and smoother substrate surfaces. Chemical mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it offers a superior means of removing unwanted topography in interlevel dielectric layers and achieving sufficient pl... » read more

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