A new technical paper, “NL2GDS: LLM-aided interface for Open Source Chip Design,” was published by researchers at University of Bristol and Rutherford Appleton Laboratory.
Abstract
“The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS’85 and ISCAS’89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.”
Find the technical paper here.. March 2026.
Eland, Max, Jeyan Thiyagalingam, Dinesh Pamunuwa, and Roshan Weerasekera. “NL2GDS: LLM-aided interface for Open Source Chip Design.” arXiv preprint arXiv:2603.05489 (2026).
Really good read! Exciting to see increased capability of open source tools powered by AI.