Power Reduction In A Constrained World


Back when 40-28nm were new, leakage power for wireless designs dominated the optimization technology focus. This led to multiple VT optimization and power intent management for digital designs to minimize or shut off leakage. As wireless devices moved to FinFET nodes, dynamic power became dominant. As a result, optimization technology focus shifted to build up dynamic techniques to complement y... » read more

Getting Ahead With Early Power Analysis


Today’s mobile applications need to cater to a broad set of applications. They can be communications-heavy (Bluetooth and GPS), graphics-intensive (streaming 4K videos), or compute-intensive workloads (AR/VR gaming). At the heart of this processing lies the all-powerful mobile processor, which includes a multi-core CPU, GPU, memory and other IP and subsystems for performing a variety of ta... » read more

Pros, Cons Of ML-Specific Chips


Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. To view part one, click here. Part two is here. SE: Is the industry's knowledge of machine learning keeping up with th... » read more

Design Reuse Vs. Abstraction


Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Abstraction Aging


During the course of doing interviews for my article on system simulation and abstraction, I spoke to several people who, just like myself, had started their career pushing abstraction. At the time, we were all frustrated that the industry didn't move fast enough. The advantages of abstraction appeared to be so clear. Everyone developed slides showing that the cost to fix bugs increased the fur... » read more

Tech Talk: FPGA RTL Checking


Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA. https://youtu.be/0N1PDYyq0dY » read more

Synopsys’ Vision For The New Wave Of Chip Design


Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

Achieving RTL-To-Netlist Equivalence


Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

Accounting For Power Earlier


Concerns about power usage in an SoC are far from new, but the adoption of power management techniques still varies by company and by project. Leading semiconductor providers have made the necessary changes in tooling and methodology to account for [getkc id="106" kc_name="power awareness"] because they have to, but the rest of the industry hasn't necessarily caught up. “The companies t... » read more

Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

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