tag: RTL

Creating Agentic EDA Methodologies
By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)
By Technical Paper Link - 09 Mar, 2026 - Comments: 1

A new technical paper, "NL2GDS: LLM-aided interface for Open Source Chip Design," was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract "The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier
By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

DFT Shifts Further Left
By Ed Sperling - 08 Dec, 2025 - Comments: 0

Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

Top Five Trends In RTL Signoff
By Suresh Babu Barla - 30 Oct, 2025 - Comments: 0

By Suresh Babu Barla and Rimpy Chugh The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage occurs far too late in the design development process. At this point, addressing such problems demands significant effort, primarily because most design-r... » read more

In-NAND Self-Encryption Architecture In A 4D-NAND Structure (DGIST, Georgia Tech Et Al.)
By Technical Paper Link - 12 Aug, 2025 - Comments: 0

A new technical paper titled "FlashVault: Versatile In-NAND Self-Encryption with Zero Area Overhead" was published by researchers at DGIST, Georgia Tech, POSTECH, Samsung Electronics, Virginia Tech, and Korea University. Abstract "We present FlashVault, an in-NAND self-encryption architecture that embeds a reconfigurable cryptographic engine into the unused silicon area of a state-of-the-ar... » read more

GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores
By Technical Paper Link - 26 Jun, 2025 - Comments: 0

A new technical paper titled "TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs" was published by researchers at University of Connecticut and University of Minnesota. Abstract "hip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being utilized. The use of th... » read more

Evaluation of LLMs on HDL-Based Communication Protocol Generation (U. of Illinois Urbana, CISPA)
By Technical Paper Link - 10 Jun, 2025 - Comments: 0

A new technical paper titled "ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols" was published by researchers at University of Illinois Urbana Champaign and CISPA Helmholtz Center for Information Security. Abstract "Recent advances in Large Language Models (LLMs) have shown promising capabilities in generating code for general-purpose programming languages. ... » read more

Innovus+ Synthesis And Implementation System
By Cadence - 14 May, 2025 - Comments: 0

The Innovus+ platform incorporates Innovus synthesis and Innovus implementation capabilities, all integrated into one unified environment for outstanding ease of use and power, performance, and area (PPA) results. Innovus+ Synthesis can be used standalone to generate physically aware netlists ready for handoff to other design teams, such as ASIC partners, or the implementation flow can conti... » read more

Formal Verification of Security Properties On RTL Designs
By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. Abstract: "Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from unknown vulnerabilities. Thus... » read more

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