tag: RTL

RTL Restructuring Issues
By Ed Sperling - 18 Jul, 2023 - Comments: 0

Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. Jim Schultz, product marketing manager for digital design implementation at Synopsys, talks about grouping and ungrouping, re-parenting, and breaking connec... » read more

Ditch The Glitch
By Ramsay Allen - 11 Jul, 2023 - Comments: 0

To support the ever-growing performance demands of cutting-edge applications like automotive and hyperscaler, SoC complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To keep up with these demands, design-for-test (DFT) logic must also evolve to ensure greater levels of test robustness and silicon health. The “Shift left” concept which... » read more

AI Adoption Slow For Design Tools
By Brian Bailey - 01 May, 2023 - Comments: 0

A lot of excitement, and a fair amount of hype, surrounds what artificial intelligence (AI) can do for the EDA industry. But many challenges must be overcome before AI can start designing, verifying, and implementing chips for us. Should AI replace the algorithms in use today, or does it have a different role to play? At the end of the day, AI is a technique that has strengths and weaknesses... » read more

Can AI Write RTL?
By Brian Bailey - 01 May, 2023 - Comments: 0

Just a few months ago, generative AI was just a promise about what would be possible in the future. Today, nearly everyone with an ounce of curiosity has tried ChatGPT. Most people appear to be somewhat impressed with what it can do, but at the same time see the limitations that it has. As Dean Drako, founder of several companies, told me: "Recently, I needed to write a patent. I described t... » read more

Hardware-Accelerated RTL Simulator
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A technical paper titled "Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism" was published by researchers at EPFL, University of Tokyo, Sharif University, and Indian Institute of Technology. Abstract "The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of thi... » read more

Logic Locking at the RTL, Leveraging The Behavioral State Transition Coding For Obfuscation (University of Florida)
By Technical Paper Link - 25 Mar, 2023 - Comments: 0

A new technical paper titled "ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach" was published by researchers at University of Florida, Gainesville, FL. Abstract: "Hardware obfuscating is a proactive design-for-trust technique against IC supply chain threats, i.e., IP piracy and overproduction. Many studies have evaluated numerous techniques for obfuscation purposes. Neverth... » read more

FPGAs: Automated Framework For Architecture-Space Exploration of Approximate Accelerators
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A technical paper titled "autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems" was published (preprint) by researchers at TU Wien, Brno University of Technology, and NYUAD. Abstract "Generation and exploration of approximate circuits and accelerators has been a prominent research domain exploring energy-efficiency and/or performance... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)
By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

Hardware Fuzzing (U. of Michigan, Google, Virginia Tech)
By Technical Paper Link - 18 Dec, 2022 - Comments: 0

A technical paper titled "Fuzzing Hardware Like Software" was published by researchers at University of Michigan, Google and Virginia Tech. The paper was presented at the 2022 Usenix Security Symposium. Abstract: "Hardware flaws are permanent and potent: hardware cannot be patched once fabricated, and any flaws may undermine even formally verified software executing on top. Consequently, ve... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows
By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

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