Author's Latest Posts

Effective Monitoring, Test, and Repair of Multi-Die Designs

Despite clear advantages, there are numerous new challenges that need to be addressed for successful multi-die realization. The multi-die test challenges include: Bare chiplet level (pre-bond) Probe, dedicated/functional pads for test Test, diagnosis, and repair Interconnects (mid/post-bond) Die-to-die test access Lane test, diagnosis, and repair Multi-die ... » read more

Holistic Verification and Validation of Automotive IP for Functional Safety SoCs

Automotive functional safety systems have strict requirements to help avoid damages to life and property in case of a failure. As technology becomes more complex, there are increasing safety-related risks from systematic failures and random hardware failures that must be considered during product development. Standards like ISO 26262 provide guidance to mitigate such safety-related risks, by de... » read more

Accelerate Test Regressions with Synopsys VIP Using Dynamic Test Loading in VCS

Functional verification ensures that a design meets its specification requirements. The initial 80% of the verification process significantly impacts the time needed to complete the final 20%, which involves extensive test scenarios and regression testing, often consuming substantial engineering resources. Typically, the desired scenario emerges late in the test case, often in the last minutes ... » read more

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software

PCI Express (PCIe) 5.0 silicon characterization across process, voltage, and temperature variations, is necessary for accelerating SoC designs. To measure key qualifying parameters, designers and test engineers must have a good understanding of the PCIe 5.0 base electrical specification and know the physical layer’s design architecture and features for accurate characterization of 32GT/s PHY ... » read more

2024 Open Source Security And Risk Analysis Report

This report offers recommendations to help creators and consumers of open source software manage it responsibly, especially in the context of securing the software supply chain. Whether a consumer or provider of software, you are part of the software supply chain, and need to safeguard the applications you use from upstream as well as downstream risk. In the following pages, we e... » read more

A Unified Solution for End-to-End Low Power Verification

Low power designs are becoming increasingly prevalent in modern electronic systems, driven by the need for energy-efficient devices. Ensuring the correctness of these designs is paramount, as even minor errors can lead to catastrophic consequences. To achieve verification closure for low power designs, a combination of static verification, dynamic simulation-based verification, formal verificat... » read more

2024 Open Source Risk In M&A By The Numbers

Here’s what we know: Most of today’s codebases contain open source components. Vulnerabilities and licensing issues in codebases are as pervasive as open source itself. Unpatched software vulnerabilities are one of the biggest cyberthreats organizations face. Failure to comply with open source licenses can put businesses at significant risk of litigation and threat to IP. T... » read more

How To Scale Application Security Across The Enterprise

Enterprise organizations have hundreds of developers on numerous teams in dozens of business units. They are all working on thousands of applications, releasing software in very rapid iteration cycles. The challenges of development across all these software development life cycles, business units, and organizational silos are well known, and the sheer scale of enterprise development multiplies ... » read more

IC Compiler II: Finding The Best Floorplan, Fast

As designers strive to pack more and more functionality into todays’ SoC’s, design size (in terms of the number of transistors packed into a chip) is growing almost exponentially. This growth brings with it an unbounded increase in not just the technical complexity of performing the physical layout of the design due to capacity challenges, but also requires designers to make choices that ca... » read more

Unlocking PPA Benefits of Backside Routing

The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

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