Author's Latest Posts


Top Considerations For Evaluating The Tech In Tech M&A


M&A is high stakes. With thousands of transactions and billions of dollars spent on technology mergers and acquisitions every year, acquirers must protect their investments by conducting due diligence. This white paper discusses: Risks you may encounter in an M&A transaction involving software; How to evaluate these risks using a multifaceted evaluation model; What to look... » read more

Choosing the Right Photonic Design Software


There are many factors to consider before deciding which photonic design software to use. To narrow the field, it can be helpful to ask these key questions as you investigate and compare software functionality. • Does the software provide enough flexibility to model and analyze products that offer the best solution to likely and possible design goals? • Is the simulation capable of pr... » read more

Securing The Mobile IoT


It’s 2019. Security fears, locked ecosystems, and lack of technology are keeping IoT products within WiFi networks, and not reaching their full potential. As an industry, we must provide IoT solutions that are simple and keep consumers--and their data--secure.The mobile IoT is the next frontier in the connected device market, providing out-of-the-box connectivity with security from silicon... » read more

FPGA Implementation Tools


Advances in design and manufacturing technology allow increased factory automation, where tasks are automatically performed by sophisticated equipment such as industrial robots. Manufacturing processes require fail-safe mechanisms to prevent human injury or costly downtime. With increasing sophistication and automation of the manufacturing processes, there is increasing need for error detection... » read more

Joint Optimization Of Hardware And Compiler


ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking. This presentation proposes a novel approach for joint optimization of algorithms/compilers and hardware architecture. The top-down/integrated approach that leverages the latest machine learning framework/compile... » read more

Redefining Expectations for Test


New and rapidly expanding applications, such as artificial intelligence and automotive, are increasing in design size and complexity. These evolving market segments require unprecedented levels of quality and long-term reliability, which has created a fundamental shift in both the importance and need for integration of advanced semiconductor test. Synopsys unveiled a new family of test products... » read more

Accelerating Physical Verification Productivity for Advanced Node Designs with IC Validator


Applications such as deep-learning, autonomous driving vehicles, and mobility on 5G networks fuel the need for continuous advancements in IC integration. Growing design complexity, pressure on design cycle time, process advancements and increasing verification requirements are driving the need for faster, more efficient physical verification flows. The current state-of-the-art FinFET processes ... » read more

Redefining Expectations For Test


New and rapidly expanding applications, such as artificial intelligence and automotive, are increasing in design size and complexity. These evolving market segments require unprecedented levels of quality and long-term reliability, which has created a fundamental shift in both the importance and need for integration of advanced semiconductor test. Synopsys unveiled a new family of test products... » read more

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism


Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User Survey, “Verification taking longer than planned” is the top reason for tapeout delays, and “Simulation runtime performance” is the top challenge for verification. Since regression test turn-a... » read more

Accelerating Toshiba’s SoC Design with Fusion Compiler


This white paper discusses how Toshiba and Synopsys worked closely to bring-up Fusion Compiler and deploy it throughout Toshiba's advanced proprietary Tachyon Design System. With improved power, performance, and area (PPA), faster time-to-results and a predictable design flow have been validated on the latest, differentiated automotive SoC ASIC products, and Fusion Compiler is being broadly dep... » read more

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