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Achieve 10X Faster CDC Debug Leveraging Machine Learning


Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of asynchronous clock and reset domains is growing heavily within these complex SoCs, leading to millions of clock domain crossing (CDC) violations at the SoC level. Each of these violations ... » read more

What Designers Need To Know About USB Low-Power States


In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond t... » read more

Reducing Simulation Regression Turnaround Time With Dynamic Performance Optimization


No single step in the development of semiconductor devices is more sensitive to speed than functional simulation. A modern system-on-chip (SoC) design simulates billions of cycles of operation in the process of completing the verification plan and achieving coverage goals. To validate full system functionality, many of these simulations include running code on one or more embedded processors. E... » read more

Securing Next-Gen 5G And IoT With Defensics Fuzzing


Expansion of the IoT brings new security challenges The evolution of 5G technologies continues to drive advancement in Internet of Things (IoT) devices and their applications. By 2025, experts predict there will be nearly 4 billion IoT mobile connections in the world, and more than 64 billion IoT devices by 2026. In addition to enabling superior performance and efficiency, 5G expands the ... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes


This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

Adding Differentiating Value And Reducing IP Integration Time for Your SoC


In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

Software Self-Test As A Safety Mechanism For Processing Units


The growing dependency of modern automobiles on electronic functions increases the need for a variety of integrated circuits (ICs) for safety-critical applications. Requirements coming from different in-car subsystems drives the need for chip manufacturers to create a wide range of specialized solutions. This, in turn, raises the bar for automotive IP suppliers and pushes them to offer configur... » read more

Radiation Tolerance Is Not Just For Rocket Scientists


As technology scales, soft errors from particle radiation are becoming increasingly concerning for in-field reliability. These radiation effects are called Single Event Upsets (SEU) and the frequency of the failures due to SEUs is known as the Soft Error Rate (SER). Soft errors are failures due to external sources. By contrast, hard errors refer to actual process manufacturing defects or electr... » read more

How Low Can You Go? Pushing The Limits Of Transistors


Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when the device is not active (leakage power). This highly competitive industry provides significant rewar... » read more

Modeling Silicon Photonics Process Parameter Variations In Synopsys OptoCompiler-OptSim


Silicon photonics (SiPh) refers to the enablement of photonic integrated circuits (PIC) over silicon wafer. SiPh enables compatibility with existing CMOS manufacturing infrastructure for large-scale integration and brings the associated benefits to the photonics, namely, lower footprint, lower thermal effects, and co-packaging of electronics and photonics on the same chip. One of the side-effec... » read more

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