Author's Latest Posts


Accelerating Physical Verification Productivity for Advanced Node Designs with IC Validator


Applications such as deep-learning, autonomous driving vehicles, and mobility on 5G networks fuel the need for continuous advancements in IC integration. Growing design complexity, pressure on design cycle time, process advancements and increasing verification requirements are driving the need for faster, more efficient physical verification flows. The current state-of-the-art FinFET processes ... » read more

Redefining Expectations For Test


New and rapidly expanding applications, such as artificial intelligence and automotive, are increasing in design size and complexity. These evolving market segments require unprecedented levels of quality and long-term reliability, which has created a fundamental shift in both the importance and need for integration of advanced semiconductor test. Synopsys unveiled a new family of test products... » read more

Building Bridges: A New DFT Paradigm


By Robert Ruiz Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today (think smartphones, laptops, televisions, etc.) contain hundreds to thousands of interconnected scan chains used to verify that the semiconductors were manufactured without defect... » read more

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism


Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User Survey, “Verification taking longer than planned” is the top reason for tapeout delays, and “Simulation runtime performance” is the top challenge for verification. Since regression test turn-a... » read more

Accelerating Toshiba’s SoC Design with Fusion Compiler


This white paper discusses how Toshiba and Synopsys worked closely to bring-up Fusion Compiler and deploy it throughout Toshiba's advanced proprietary Tachyon Design System. With improved power, performance, and area (PPA), faster time-to-results and a predictable design flow have been validated on the latest, differentiated automotive SoC ASIC products, and Fusion Compiler is being broadly dep... » read more

Enterprise or Open Source: Which SAST Tool Is Right for You?


Static application security testing (SAST) is an essential part of any secure development workflow. But not all SAST tools are created equal. It’s crucial that you weigh your options carefully when choosing a SAST tool to avoid unnecessary costs in the future. This white paper compares open source and enterprise SAST solutions and provides relevant information to help you select the option th... » read more

Efficient Low-Cost Implementation of NB-IoT for Smart Applications


NB-IoT is an emerging technology for narrowband wireless communication standardized by 3GPP. It has been designed with a focus on minimizing end-user equipment processing requirements and power consumption to enable the massive deployment of low-cost devices for a broad range of smart applications. This white paper highlights the key challenges of NB-IoT modem design. It proposes a hardware/sof... » read more

Digital Signal Processing for Frequency-Modulated Continuous Wave RADARs


RADAR, LiDAR and vision systems play a critical role in enabling advanced driver-assistance systems (ADAS) and autonomous driving (AD). The automotive ADAS markets are forecast to grow at high rates in the upcoming years, with increasing requirements and system implementation complexity. This paper provides an overview of RADAR technology as used in ADAS applications, including a summary of the... » read more

Open Source in M&A Due Diligence


Most companies involved with technology M&A understand the danger of open source risks in software. Today’s software contains significant amounts of open source—on average more than 50%, according to a 2018 Synopsys report. There are several ways to assess and manage open source risk in a transaction, with some more effective than others. Similarly, there are several approaches to open s... » read more

A Simplified Way to Debug IIP Designs and SoC


Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

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