Author's Latest Posts


Maximizing Coverage Metrics with Formal Unreachability Analysis


Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the proce... » read more

12 Levers to Elevate Your Software Testing


Software dominates automotive functions. Superior product and software quality are the key to high customer satisfaction, meeting safety requirements, and conquering tough timelines. The challenge is how to achieve maximum software quality without hiring an army of testers. This checklist describes 12 levers you can pull to help you build the most effective test team, while making your tes... » read more

Enabling Efficient Multi-Die Design Implementation and IP Integration


Many industry trends are driving chip developers to consider multi-die designs using advanced 2.5D and 3D technologies. Such designs enable incorporating heterogeneous and homogeneous dies in a single package, increasing density while reducing signal propagation times. However, multi-die designs introduce new challenges that must be addressed by all relevant electronic design automation (EDA) a... » read more

Requirements and Best Practices for Trustworthy Automotive Semiconductors


The complexity of electronic systems supporting Advanced Driver Assistance Systems (ADAS), Highly Automated Driving (HAD), and in-vehicle infotainment is growing exponentially. This, together with the move from multiple domain-specific Electronic Control Units (ECUs) to a zonal architecture will require high-performance computing. Furthermore, new use cases for Battery Electric Vehicles (BEV) i... » read more

Unifying Storage Diversity: Leveraging PCIe IP for Multi-Device, Multi Form Factor Designs


In the fast-paced world of data storage, designers are racing to keep up with ever-evolving interface standards and form factors. This whitepaper explores the impact of these industry shifts, focusing on the integration of PCIe interfaces within the context of varying storage device form factors like the Enterprise and Datacenter Standard Form Factor (EDSFF). PCIe designs need to be flexible in... » read more

Effective Monitoring, Test, and Repair of Multi-Die Designs


Despite clear advantages, there are numerous new challenges that need to be addressed for successful multi-die realization. The multi-die test challenges include: Bare chiplet level (pre-bond) Probe, dedicated/functional pads for test Test, diagnosis, and repair Interconnects (mid/post-bond) Die-to-die test access Lane test, diagnosis, and repair Multi-die ... » read more

Holistic Verification and Validation of Automotive IP for Functional Safety SoCs


Automotive functional safety systems have strict requirements to help avoid damages to life and property in case of a failure. As technology becomes more complex, there are increasing safety-related risks from systematic failures and random hardware failures that must be considered during product development. Standards like ISO 26262 provide guidance to mitigate such safety-related risks, by de... » read more

Accelerate Test Regressions with Synopsys VIP Using Dynamic Test Loading in VCS


Functional verification ensures that a design meets its specification requirements. The initial 80% of the verification process significantly impacts the time needed to complete the final 20%, which involves extensive test scenarios and regression testing, often consuming substantial engineering resources. Typically, the desired scenario emerges late in the test case, often in the last minutes ... » read more

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software


PCI Express (PCIe) 5.0 silicon characterization across process, voltage, and temperature variations, is necessary for accelerating SoC designs. To measure key qualifying parameters, designers and test engineers must have a good understanding of the PCIe 5.0 base electrical specification and know the physical layer’s design architecture and features for accurate characterization of 32GT/s PHY ... » read more

2024 Open Source Security And Risk Analysis Report


This report offers recommendations to help creators and consumers of open source software manage it responsibly, especially in the context of securing the software supply chain. Whether a consumer or provider of software, you are part of the software supply chain, and need to safeguard the applications you use from upstream as well as downstream risk. In the following pages, we e... » read more

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