Author's Latest Posts


Lower Process Nodes Drive Timing Signoff Software Evolution


A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Build Security Into Your SDLC With Coverity


Are your developers getting discouraged by too many false positives from security tools that slow them down? You need a solution that boosts their productivity, finds real vulnerabilities, and provides expert remediation guidance. Coverity will help you achieve this and more. Learn about Coverity’s unique technical capabilities and why it should be your go-to solution for static analysis secu... » read more

Monte Carlo Analysis Using Synopsys Custom Design Platform


In this 5th video of the series, Kai Wang, Director of Engineering at Synopsys, explains the need of Monte Carlo to improve yield, and how designers use advanced features like variation scoping and sigma amplification to avoid costly MC simulations. Click here to watch this video white paper. » read more

Early Verification Of Multi-Cycle Paths And False Paths In Simulation


Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “... » read more

Importance of Dependent Failure Analysis For Safety-Critical IP And SoCs


This white paper explains the importance of implementing DFA in the automotive IP and SoC development cycle and how DFA helps meet the technical independence essentials according to the design’s safety requirements. To read more, click here. » read more

Verifying Safety-Critical FPGA Designs With Fault Simulation


Supporting safety and assurance in designs, such as the chips used in industrial, aerospace and defense applications, requires more than traditional functional verification. Even if every bug is found and fixed before release, these applications have additional requirements for functional safety. They must be able to handle a variety of faults and induced errors, either by correcting them or by... » read more

Virtual Prototyping For Electric Vehicles: From System To Software


Road vehicles have long been considered one of the most challenging types of development projects. The tight interaction between electrical and mechanical components and the inherent safety requirements of high-speed/high-power operation are just the baseline issues. Layered on top of that are the many challenges of the physical environment: wide temperature and humidity range, noise, vibration... » read more

USB4: User Expectations Drive Design Complexity


This white paper outlines the capabilities of USB4 Hosts, Hubs, Docks, and Devices with an emphasis on how end-user expectations drive the complexity of USB4 products. USB4 is the most complex USB specification so far and requires designers to understand the USB4, USB 3.2, USB 2.0, USB Type-C, and the USB Power Delivery specifications. Designers must also understand PCIe and DisplayPort specifi... » read more

Machine Learning — Everywhere: Enabling Self-Optimizing Design Platforms


Machine-learning offers opportunities to enable self-optimizing design tools. Very much like self-driving cars that observe real-world interactions to improve their responses in different (local) driving conditions, AI-enhanced tools are able to learn and improve in (local) design environments after deployment. These new, ML-driven capabilities can be embedded in different design engines, gi... » read more

Shift Left Verification With Comprehensive Lint Signoff


With soaring complexity and continuously increasing chip sizes, achieving efficient and predictable design closure has become a prominent challenge among designers today. Demand for a faster time to market is forcing designers to find ways to shorten design cycles with accurate, efficient, one-time RTL to silicon. To meet these requirements designers are looking to implement early ”shift left... » read more

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