tag: physical design

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)
By Technical Paper Link - 09 Mar, 2026 - Comments: 1

A new technical paper, "NL2GDS: LLM-aided interface for Open Source Chip Design," was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract "The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (... » read more

Multimodal LLM Assistant for Chip Physical Design (National Taiwan Univ., UCLA, NVIDIA)
By Technical Paper Link - 28 Oct, 2025 - Comments: 0

A new technical paper titled "Multimodal Chip Physical Design Engineer Assistant" was published by researchers at National Taiwan University, University of California, Los Angeles and NVIDIA Research. Abstract "Modern chip physical design relies heavily on Electronic Design Automation (EDA) tools, which often struggle to provide interpretable feedback or actionable guidance for improving ro... » read more

Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes with High Core Density (Politecnico di Torino, imec et al.)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes" was published by researchers at Politecnico di Torino, EPFL, National Technical University of Athens and imec. Abstract "This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), address... » read more

A New RF Platform For Silicon MMIC And System Design
By Cadence - 04 Jun, 2025 - Comments: 0

Next generation wireless modules combine innovative and proven RFIC/MMIC designs into a single package―delivering superior performance, lower power consumption, and reduced size, weight, and cost. Advanced system engineering plays a crucial role in this progress, with a strong focus on packaging interconnect design, RF analysis, and thermal and electromagnetic (EM) awareness that enable se... » read more

Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies" was published by researcher at the Technical University of Munich (TUM). Abstract "As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field... » read more

Hyperconvergence Of Design For Test And Physical Design
By Sri Ganta - 11 Feb, 2025 - Comments: 0

By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 1

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management
By Jeff Wilson - 20 Jul, 2023 - Comments: 0

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’... » read more

RTL Restructuring Issues
By Ed Sperling - 18 Jul, 2023 - Comments: 0

Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. Jim Schultz, product marketing manager for digital design implementation at Synopsys, talks about grouping and ungrouping, re-parenting, and breaking connec... » read more

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