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ECO Should Not Stand For Extended Challenge Order


There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such task. Ideally, when the design has been placed and routed (physical implementation), final analysis of timing and other metrics is performed and an engineering change order (ECO) file is issued to t... » read more

Cutting Clock Costs On The Bleeding Edge Of Process Nodes


In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and pre-silicon verification costs are doubling each process leap. As companies leap from node to leading node, a natural question arises. Why is it becoming harder and more expensive to tapeout a chi... » read more

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow


The FICS Research Institute (University of Florida) has published a new research paper titled "Secure Physical Design." This is the first and most comprehensive research work done in this area that requires significant attention from academia, industry, and government for ensuring trust in electronic design automation flow," said lead author Sukanta Dey. Abstract "An integrated circuit is s... » read more

Optimizing For Energy In Physical Design


Energy is a precious resource, which should not be wasted. Energy drives economies and sustains societies. Predictions show that the energy of electronics may soon consume 20% to 33% of the global energy supply, as it is highlighted in this blog post about "Design and Manufacturing in 2030" from Greg Yeric, fellow at Arm. Energy efficiency is such an important global issue that it is ... » read more

Place And Route Made Easier And Faster


By Allan Crone A predictable trend in IC design is the ever-increasing size and complexity of designs while keeping the time allocated for the projects the same or shorter. Along with the tape-out pressure, organizations need to find cost savings everywhere possible. Lowering the overall cost of ownership of EDA tools is a viable way to manage the design budget. Consequently, design teams ar... » read more

Can Machine Learning Chips Help Develop Better Tools With Machine Learning?


As we continue to be bombarded with AI- and machine learning-themed presentations at industry conferences, an ex-colleague told me that he is sick of seeing an outline of the human head with a processor in place of the brain. If you are a chip architect trying to build one of these data-centric architecture chips for machine learning or AI (as opposed to the compute-centric chips, which you pro... » read more

I Say ‘High’ [Performance], You Say ‘Low’ [Power]


“…You say ‘why’, and I say ‘I don’t know…’” Actually, I do know. Everybody loves a high-performance product. Even just hearing that a product is high-performance sets higher expectations than if the product is simply described as “fast” or “powerful.” When it comes to SoC design, “high-performance” refers to a set of designs that run at very high clock freque... » read more

The Perfect (Silicon) Marriage… Yes, It Exists


Nope, this is not Dr. Phil masquerading as a tech blogger, trying to penetrate the semiconductor market. I am no Dr. Phil, but today, rather than expound on interconnect IP and how it relates to the various trends, applications, markets, etc., I would like to tell you a story about a relationship and share an experience with one of our customers, a leading manufacturer of autonomous systems. ... » read more

Leading Chip Maker Rolls Out SoC For Automotive Market With NetSpeed Gemini


There is tremendous growth in the automotive IC market due to the trend towards electric or hybrid cars and applications for enhanced safety. However, the technical challenges of implementing today's connected car and the autonomous vehicles of the future are daunting. To read more, click here. » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning


Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

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