A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management

Implementing correct by construction and DRC-clean layout modifications.


The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’s not really meant to do.

Three key metrics for any integrated circuit (IC) design are the power, performance, and area (PPA) targets. Over-design the power grid, and you waste precious area. Under-design, and your IC may never achieve its designed voltage (IR) drop levels and electromigration (EM) protection requirements. The solution? Design the power grid to be efficient for the majority of the design, then apply layout enhancements to optimize specific areas in the layout that must support greater power usage.

However, P&R tools are built to place logic cells and route the connections in digital IC layouts. Custom design tools allow designers to implement intricate analog IC layouts. Most custom design and P&R tools provide some add-on functionality to enable engineers to make changes to layouts, but that’s not what they were designed to do. Applying layout modifications during custom design or digital IC implementation to improve power management is typically a difficult, laborious process, just like trying to hammer that nail with a rock. Using these tools to perform layout modification processes for which they were never intended is time-consuming, and you still end up with less than optimal results from both a quality of results and performance perspective. Until now, though, there really hasn’t been an alternative.

Automated design-stage layout optimization

The Calibre DesignEnhancer tool from Siemens EDA provides multiple layout modification use models that enable design teams to implement layout optimizations during custom design and digital IC implementation that are automated, analysis-based, and correct-by-construction. Built on the Calibre nmPlatform, the Calibre DesignEnhancer tool leverages foundry-preferred Calibre design rule decks, Calibre connectivity data, and industry-leading runtimes to improve both design team productivity and design quality.

The Calibre DesignEnhancer tool currently provides three use models:

  • Via insertion to reduce IR drop and moderate the impact of via resistance on manufacturability and reliability
  • Parallel run lengths insertion to lower resistance on power grid structures
  • Filler cell and DCAP cell insertion to prepare designs for physical verification

Via insertion

The Calibre DesignEnhancer Via use model automatically maximizes the insertion of DRC-clean vias on user-specified nets based on two drivers—insertion rate and runtime (figure 1). Via prioritization and multiple via configurations improve the manufacturing robustness of a design. Available via operations include both multi-layer checks (such as enclosure and extension rules) and single-layer spacing and width-based count checks.

Fig. 1: Automated via insertion using the Calibre DesignEnhancer Via use model maximizes the insertion of DRC-clean sign-off quality vias.

A Calibre DesignEnhancer Via kit accesses in-depth knowledge of complex process node design rules within the Calibre nmPlatform, such as net type spacing, parallel run length, via count, and connectivity, to ensure DRC-clean vias are added at the highest insertion rate. The Calibre DesignEnhancer Via use model works with any Via kits provided by the foundries for their technology processes, providing flexibility across multiple process nodes.

Parallel run lengths insertion

The Calibre DesignEnhancer Pge use model automatically finds open tracks and inserts DRC-clean metal and vias to create parallel runs. While the Pge use model (figure 2) can run efficiently at the block or chip level, best practice is to use an EMIR analysis tool to focus these layout enhancements in specific areas to achieve maximum reduction in IR drop in those areas while limiting overall impact on timing.

Fig. 2: The Calibre DesignEnhancer Pge use model automatically inserts DRC-clean metal and vias in open areas to help lower resistance on power grid structures.

Filler and DCAP cell insertion

The Calibre DesignEnhancer Pvr use model replaces time-consuming and limited P&R filler cell insertion processes with push-button insertion of correct-by-construction filler cell and DCAP cell insertion in IC layouts after design implementation (figure 3). Design teams can ensure DRC-correct layouts while significantly reducing filler cell and DCAP cell insertion runtimes. Over the span of a design flow, the Calibre DesignEnhancer Pvr use model enables design teams to begin signoff physical verification much earlier, resulting in both faster time to tapeouts and higher quality designs.

Fig. 3: The Calibre DesignEnhancer Pvr use model automatically adds filler and DCAP cells to prepare designs for physical verification.

User-friendly integration and functionality

As part of the Calibre nmPlatform, the Calibre DesignEnhancer tool seamlessly integrates with all major IC design and P&R tools to provide signoff-quality solutions earlier and faster in the design and verification flow (figure 4).

Fig. 4: The Calibre DesignEnhancer tool is integrated with all leading design and P&R tools to provide a consistent interface and use model.

Push-button usability shields designers from low-level operational details and tasks, making the Calibre DesignEnhancer tool easy to use. Native support for GDS and OASIS formats and the ability to directly read the industry standard LEF/DEF format ensures interoperability in all environments. Layout modifications can be output to an incremental DEF file for fast, accurate back-annotation of changes to the design database to enable power and timing analysis using preferred signoff tools. Automated generation of a modified GDS/OASIS file allows design teams to begin physical verification runs sooner.


The faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing design modifications to reduce IR drop and EM and prepare for physical verification. Design teams can quickly and easily implement multiple layout optimizations, while knowing all changes will be correct by construction and DRC-clean because they are based on a thorough understanding of available open areas and Calibre signoff DRC rules. This ease of use combined with fast runtimes helps design teams get from design implementation to signoff physical verification faster, with confidence in the results. The right tool does make all the difference!

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