3 Ways To Improve Design Collaboration: Part 2


In the last blog in this series, we talked about how VDD can help design and layout engineers work more efficiently. Communicating precise and accurate information is a key factor in improving productivity, estimates, and the planning process. Visualizing the changes makes it easier to follow the technical details. The ECO (Engineering Change Order) phase is an important phase in the lifecycle... » read more

Layout Generators For Artificial Intelligence Hardware Design


Artificial intelligence (AI) is a powerful tool that offers great convenience in many areas of life. In addition to improving Internet searches and online shopping, it enables driver assistance systems that can save lives, for example. AI in its various forms is the essential tool for such applications, and it can be expected to show a similar development as microelectronics did. Although AI... » read more

Visually Assisted Layout In Custom Design


Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Fast-Track Your Early SoC Design Exploration And Verification


By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

Getting To Tape-Out Quicker With Analog Layout Generators


All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands ... » read more

Speed Up P2P Resistance Debugging With Selective Highlighting


Point-to-point (P2P) resistance simulation calculates the effective parasitic resistance from one or more specified points (sources) to another set of points (sinks) on an integrated circuit (IC) layout. The results of these simulations are a key component in the verification of the robustness and reliability of IC layout interconnect—designers must have this information to accurately perform... » read more

Thermal Impact On Reliability At 7/5nm


Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

More Nodes, New Problems


The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

8 Checks That Every PCB Designer Needs To Achieve Electrical Sign-Off


Automate electrical design rule checking (DRC) for fast, cost-effective PCB design verification. These eight rules apply regardless of your PCB layout tool or level of expertise. To read more, click here. » read more

LVS Boxing Helps Designers Knock Out Designs Quickly


Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

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