Analog Chip Layout: Creativity Vs. Deadlines

On the tension between creative, precise high-end layouts and firmly established tapeout deadlines.


The entire design of integrated circuits, from the specification onward, depends on successful validation by measurement of microchips.

One key milestone in this process is the completion of the layout. However, the path to reach this point can be quite difficult as many iterations are usually required. It includes:

  • Iterations with the customer to finalize the specification.
  • Iterations between architecture and IP design or IP integration to comply with the specification.
  • Iterations in circuit design to find the right topology.
  • Iterations between circuit design and layout design to eliminate all parasitic effects, determine the appropriate sizing, and comply with area and quality requirements.

This design flow is long, and it is not rare for a change to find its way into the layout “at the last minute.” This often results in frustration and errors just before tapeout. So are there ways to respond quickly and implement the required changes fast? Here are a few ideas.

Every company involved in analog design likely has more than a few scripts that support all possible design steps. These are generally very specifically customized to the problems in question and help with completing standard tasks. For example, a typical circuit can be sized more quickly, a standard sequence of tools can be executed automatically or a repetitive task in the layout can be completed rapidly. During the layout design phase in particular, such steps are often very problem-specific, and not every designer enjoys writing source code. After all, the layout process is based on graphical entry, and the work rather revolves around a mix of design expertise, aesthetics, and craftsmanship.

Depending on the willingness to invest, many different add-ons for design tools may be utilized to support tasks such as placement and routing. This is very useful, but the automatic design of the routing, in particular, requires very finely adapted constraints in order to exploit the full potential of these tools based on optimization methods. This is a demanding discipline in its own right and represents a significant hurdle in practice. Essentially this means that anyone who understands optimization also knows which constraints matter. Conversely, designers have a “gut instinct” for the relevant constraints and know how to implement these in the layout.

Ideally, experts in design and experts in electronic design automation (EDA) should collaborate in a team to improve the efficiency of the design process. This connects the specific design requirements with the possibilities of EDA, allowing for efficient identification of the most effective customization parameters for designs, scripts and design flows and – above all – ways to combine them appropriately. For example, a designer immediately will see how to partition the layout to permit efficient manual design and high-quality layout. The EDA expert then can build upon this principle and provide the right problem-specific script for quickly passing iterations and adaptations using automation.

The exciting part is that EDA often can help with problems that initially appear difficult to automate. Communication between EDA experts and design experts is therefore the key to efficient layout and design in general when time is of the essence. Contact your EDA department, and you may be surprised.

More information about the possibilities of EDA in analog IC layout can be found here.

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