Noise Abatement


[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Fusing CMOS IC And MEMS Design For IoT Edge Devices


Creating a sensor-based IoT edge device is challenging, due to the multiple design domains involved (Analog, digital, RF, and MEMS). But, creating an edge device that combines the electronics using the traditional CMOS IC flow and a MEMS sensor on the same silicon die can seem impossible. In fact, many IoT edge devices combine multiple dies in a single package, separating electronics from the M... » read more

Node Warfare?


By Mark LaPedus & Ed Sperling GlobalFoundries uncorked a 12nm finFET process, which the company said will provide a 15% increase in density and more than 10% improvement in performance over the foundry's existing 14nm process. This is GlobalFoundries' second 12nm process. It announced a 12nm FD-SOI process called 12FDX last September, although it first mentioned a 12nm process back in J... » read more

Fusing CMOS IC And MEMS Design For IoT Edge Devices


Creating a sensor-based IoT edge device is challenging, due to the multiple design domains involved (Analog, digital, RF, and MEMS). But, creating an edge device that combines the electronics using the traditional CMOS IC flow and a MEMS sensor on the same silicon die can seem impossible. In fact, many IoT edge devices combine multiple dies in a single package, separating electronics from the M... » read more

IP Biz Changes As Markets Fragment


Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"]' S... » read more

Tech Talk: Smart Manufacturing


Tom Salmon, vice president of collaborative technology platforms at SEMI, examines the electronics supply chain and what the industry organization is doing to pull all of the pieces together. https://youtu.be/jWX9mayMaZo Related Stories Smart Manufacturing Gains Momentum Problems remain for legacy infrastructure, but adoption will continue to grow as gaps are identified and plugged. ... » read more

Rethinking Computing Fundamentals


New compute architectures—not just new chips—are becoming a common theme in Silicon Valley these days. The whole semiconductor industry is racing to find the fastest, cheapest, lowest-power approach to processing. The drivers of this shift are well documented. Moore's Law is slowing down, in part because it's becoming more difficult to route signals across an SoC at the latest process no... » read more

A Tale of Two Testers


David Tacelli, president and CEO of Xcerra, was excited. His company’s reception for customers (and the press) at the Trou Normand restaurant in San Francisco’s hip South of Market neighborhood was going very well. Gourmet salames and other tasty foods were on offer, along with fine wines and craft ales and beers. He gleefully pointed out to editors that the product to be introduced at t... » read more

Finally, A Painless Solution For Analog Verification Management


Usually, teams manage analog simulations manually or they use complex and expensive tools that require intricate setup and proprietary test plans before they can be deployed. What teams need is an easy way to manage analog verification in order to track the large number of simulations for each project. Tracking simulation results at all levels for each team member and project managers requires ... » read more

Re-Using IP In Packaging


For the past decade, the promise held forth by advanced packaging was that it would allow chipmakers to mix and match analog and digital IP without worrying about the process node at which they were developed or the physical interactions between components. This is a big deal when it comes to analog. Analog IP doesn't benefit from node shrinking the way digital logic does, and in many cases ... » read more

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