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3-to-1 Reconfigurable Analog Signal Modulation Circuit On A Single Device


A new technical paper titled "Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor" was published by researchers at NaMLab gGmbH, GlobalFoundries, and TU Dresden. "Reconfigurable field effect transistors are an emerging class of electronic devices, which exploit a structure with multiple independent gates to selectively adjust the charge carrier ... » read more

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development


By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs


Device symmetry ensures accurate, efficient performance of analog and custom IC designs. However, traditional physical verification for symmetry is complex and time-consuming. Calibre interactive symmetry checking runs inside the design environment to simplify and enhance IC symmetry verification. Design teams can use Calibre interactive symmetry checking to quickly and accurately analyze layou... » read more

Graph-Based, Formal Equivalence Checking Method


A new research paper titled "Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits" was published by researchers at University of Bremen and DFKI GmbH. Abstract: "Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level met... » read more

Detailed RF Characterization of Ultra-Thin Indium Oxide Transistors


A new technical paper titled "Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure" was published by researchers at Purdue University and won the 2022 Device Research Conference Best Student Paper Award (DRC 2022 held in June). According to this Purdue University news release, "In this work, the radio frequency (RF) performance of indium oxide transistors w... » read more

Improving Design Collaboration In The Age Of Remote Work


Teams of analog and mixed signal (AMS) design and layout engineers spend countless hours extracting every ounce of performance out of their design. They continually make incremental changes daily to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to the circuit layout. As technology advances, accounting for the paras... » read more

A Multi-Level Analog IC Design Flow For Fast Performance Estimation Using Template-Based Layout Generators And Structural Models


Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower abstraction levels, conservative assumptions are usually applied that often result in suboptimal performances such as area and power consumption. In order to enable both early performance estimates ... » read more

Verification Scorecard: How Well Is The Industry Doing?


Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)


A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

DNN-Opt, A Novel Deep Neural Network (DNN) Based Black-Box Optimization Framework For Analog Sizing


This technical paper titled "DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks" is co-authored from researchers at The University of Texas at Austin, Intel, University of Glasgow. The paper was a best paper candidate at DAC 2021. "In this paper, we present DNN-Opt, a novel Deep Neural Network (DNN) based black-box optimization framework for analog sizi... » read more

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