Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Virtual System Development Platforms For Safeguarding Complex Microelectronic Systems


Electronic systems are rapidly becoming more complex. This impacts almost all domains in which electronics are used today — especially industrial applications, medical engineering, communications engineering and, of course, automotive applications. What's changed is the addition of huge numbers of sensors and actuators that interact with the environment, the local integration of highly co... » read more

IoT For Building Energy Systems In Zero-Emission Buildings


By Dirk Mayer and Olaf Enge-Rosenblatt How can buildings contribute to a significant reduction in global primary energy consumption? Due to the global trend toward reducing CO2 emissions and resource conservation, the demands are increasing with regard to the efficiency of heating, ventilation and air-conditioning (HVAC) systems operated in buildings. In conflict with calls for fas... » read more

Blog Review: Oct. 2


In a video, Cadence's Tom Hackett explains finite element analysis by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. Synopsys' Taylor Armerding examines why the 156-year-old False Claims Act has new relevance when companies are accused of failing to meet cybersecurity standards. Mentor's Colin Walls demystifies memo... » read more

Taking Energy Into Account


Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

Manufacturing Bits: Aug. 27


Holographic lithography Switzerland’s Nanotech SWHL GmbH has come out of stealth mode and disclosed its initial technology—a holographic lithography system. Founded in 2015, Nanotech SWHL has developed a sub-wavelength holographic lithography system that generates and prints 3D images on surfaces with one mask at one exposure. Still in R&D, the system is initially targeted for advanced ... » read more

Getting To Tape-Out Quicker With Analog Layout Generators


All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands ... » read more

Benchmarking Workshop On (Active) Vibration Damping


Benchmarking workshops (also called mechathons when held in the area of mechatronics) can be used to benchmark existing technologies and bring together experts of the same field in order to encourage knowledge transfer and future cooperation. Within the frameworks of the Comet K2 Research Center “Symbiotic Mechatronics“ of the Linz Center of Mechatronics (LCM) and the “Mechatronics Allian... » read more

Manufacturing Bits: July 10


Semicon West It’s Semicon West time again. Here’s the first wave of announcements at the event: Applied Materials has unveiled a pair of tools aimed at accelerating the industry adoption for new memories. First, Applied rolled out the Endura Clover MRAM PVD system. The system is an integrated platform for MRAM devices. Second, the company introduced the Endura Impulse PVD platform for P... » read more

Manufacturing Bits: June 25


Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

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