Getting To Tape-Out Quicker With Analog Layout Generators


All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands ... » read more

Benchmarking Workshop On (Active) Vibration Damping


Benchmarking workshops (also called mechathons when held in the area of mechatronics) can be used to benchmark existing technologies and bring together experts of the same field in order to encourage knowledge transfer and future cooperation. Within the frameworks of the Comet K2 Research Center “Symbiotic Mechatronics“ of the Linz Center of Mechatronics (LCM) and the “Mechatronics Allian... » read more

Manufacturing Bits: July 10


Semicon West It’s Semicon West time again. Here’s the first wave of announcements at the event: Applied Materials has unveiled a pair of tools aimed at accelerating the industry adoption for new memories. First, Applied rolled out the Endura Clover MRAM PVD system. The system is an integrated platform for MRAM devices. Second, the company introduced the Endura Impulse PVD platform for P... » read more

Manufacturing Bits: June 25


Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

What’s Next In Advanced Packaging


Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Power/Performance Bits: Mar. 19


Explainable AI Researchers from Technische Universität Berlin (TU Berlin), Fraunhofer Heinrich Hertz Institute (HHI), and Singapore University of Technology and Design (SUTD) propose a pair of algorithms to help determine how AI systems reach their conclusions. Explainable AI is an important step towards practical applications, argued Klaus-Robert Müller, Professor for Machine Learning at... » read more

Chasing Reliability In Automotive Electronics


Assuring reliability in automotive electronics has set off a scramble across the semiconductor supply chain and unearthed a list of issues for which there is insufficient data, a lack of well-defined standards, and inconsistent levels of expertise. Reliable functional safety that spans 18 to 20 years of service in harsh environments, or under constant use with autonomous taxis or trucks, is ... » read more

Making Autonomous Vehicles Safer


While self-driving vehicles are beta-tested on some public roads in real traffic situations, the semiconductor and automotive industries are still getting a grip on how to test and verify that vehicle electronics systems work as expected. Testing can be high stakes, especially when done in public. Some of the predictions about how humans will interact with autonomous vehicles (AVs) on public... » read more

Taming NBTI To Improve Device Reliability


Negative-bias temperature instability is a growing issue at the most advanced process nodes, but it also has proven extremely difficult to tame using conventional approaches. That finally may be starting to change. NBTI is an aging mechanism in field-effect transistors that leads to a change of the characteristic curves of a transistor during operation. The result can be a drift toward unint... » read more

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments


On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavio... » read more

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