Analog IP Reuse

Analog integrated circuit IP is essential to how microelectronic circuits and systems interact with the environment. It enables things like signal conversion, stable power supply, and communication in state-of-the-art devices. However, designing these critical components – even though they are often a small part of complex chips – is very costly and risk-prone. And in today’s analog field, reuse is still the exception. While the individual steps in digital design have been systematized and highly automated, analog design is still largely done by hand. So what are the options for addressing this challenge?

Let’s first take a brief look at digital design. The decisive factor for the high degree of automation are the good prospects for abstraction. Digital circuit behavior is implemented using standard basic cells and abstracted by Boolean logic. This, in turn, is at the core of hardware description languages, which are used to describe – and reuse – the detailed behavior of individual blocks up to the system architecture. On the layout side, this architecture is first suitably partitioned, the arrangement pre-planned in the floor plan, and then finally placed and routed – in each case in fully automated steps. The fact that the hardware description can be reused so well in other target technologies means the reuse of digital IP is readily implementable.

In analog, unfortunately, we have so far lacked this quality of structuring and automation and thus also the possibility to reuse IP. A core problem is the lack of abstraction. While it’s true that standard digital cells must also be designed manually, thereafter they are available as basic building blocks for digital design. In analog, on the other hand, the basic building blocks (e.g. current mirrors or differential pairs) are always created anew – and manually. In the process, details such as the dimensioning of the components and the arrangement in the layout are repeatedly adjusted by hand. Starting from these basic blocks, further design is then again done manually and very much bottom-up (instead of top-down), because there is usually no machine-readable floor plan and no top-down approach available. Instead, the floor plan is roughly sketched and each developer is given a target floor plan of the circuit based on estimates. As a result, the overall circuit is created by an entire team, and its potential for optimization becomes visible only at a very late stage after the individual blocks have been put together. This not only makes iteration loops for optimization very time-consuming, but the manual procedure and the lack of abstraction of design steps also dramatically limit IP reuse.

However, there are methods for improving IP reuse. These can help with things like creating further performance variants of an IP more quickly or progressing quickly to new process nodes. Especially when it comes to leading-edge nodes, this approach can secure the USP. On the one hand, this can be implemented in terms of design methodology, with analog designers designing their circuits in such a way that adjustments can be made relatively easily. For instance, flexible layout planning allows the layout to “grow” in defined directions at relevant points after adapted dimensioning. On the other hand, there are also some automation solutions that are partially “hidden” within the tools of the major CAD firms, and there are third-party vendors that offer EDA solutions for analog automation that improve reuse.

Let’s focus on the EDA tools in this blog post. It’s usual that every design team has at least a handful of scripts to automate everyday tasks. This is already a step in the direction of reuse, because this at least accelerates small – especially repetitive – tasks. In the market, however, EDA suppliers also offer tools for specific subtasks. The most common example is optimization, which can automatically find a suitable dimensioning based on the specifications in machine-readable optimization goals. If a circuit is now ported to a new PDK for which tools are available, especially on the schematic level, this permits good reuse of the circuits (if feasible), test benches, and optimization setups, resulting in slightly more IP reuse.

However, there are also tools for layout design that enable cross-PDK and cross-flavor reuse. For one thing, the major tool vendors are delivering better and better tools that speed up the manual design process. In some cases, these tools also allow abstract placement specifications to be saved – sometimes in the form of templates – and thus reused in subsequent projects. Specialized third-party vendors offer additional layout automation tools that complement the design tool. These tool offerings can often be combined with tailored services. This enables layout reuse, which works at the basic block level and also extends to the transfer of entire source layouts to new technology nodes.

All this shows that analog IP reuse is a complex challenge. With automation, systematic thinking, and abstraction currently still lacking, a combination of predictive design and use of niche EDA solutions is needed. It’s particularly helpful when design experts and EDA experts work together on the topic of IP reuse. If they develop a common language, they will also find the sweet spot where design requirements meet EDA capabilities. This approach not only increases efficiency in analog design, but also reduces design risk and opens the door to more reuse in analog IP design.

You can find more information about this subject at https://www.eas.iis.fraunhofer.de/en/business_areas/efficient_electronics/automation-analog-design.html.