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Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse


Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previ... » read more

Chip Design Teams And Restaurant Kitchen Staff Have A Lot In Common


By Anagha Pandharpurkar Believe it or not, electronic device and systems-design teams have a lot in common with kitchen staff in big commercial restaurants: They both leverage many different tools and resources to churn out great products in a high-pressure environment to a demanding audience that wants it now, not tomorrow. Unfortunately, design teams are often not nearly as well equippe... » read more

Maximize The Value Of Your 3rd Party IP Investment


The need to get to market sooner has resulted in significant growth in the use of 3rd party IP. This in turn has led to a growth in IP vendors. While licensing 3rd party IP may lead to reducing the development effort and time, it can potentially be costly and bring upon significant risk. Of course, there is the obvious cost of licensing the IP itself, but there are several other hidden costs... » read more

Productivity Keeping Pace With Complexity


Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Utilizing IP Lifecycle to Author IP for Successful Reuse


Successful reuse of IP relies on the entire IP lifecycle. Developing and maintaining documentation, reference designs and test suites requires a significant effort. Learn how they are vital for reuse in this white paper. Click here to read more. » read more

Tracking Re-Use Of Design IPs


Design teams have a great incentive to create design blocks or IPs that can be reused: Each time an IP is successfully reused, precious time is saved from project schedule. Of course, as easy as it sounds, achieving this goal in real life is not simple. In reality, the observation is that design libraries cannot be used as-is by multiple projects. Consider this scenario: A smart new graduate... » read more

What’s In Your IP?


Jeff Markham, software architect at ClioSoft, talks with Semiconductor Engineering about IP traceability in markets such as automotive and aerospace, what’s actually in IP, what should not be in that IP from a security standpoint, and how all of this data can used to avert system reliability issues in the future. » read more

Challenges In IP Reuse


Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

IP Management And Development At 5/3nm


The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

SOC Design & IP Management—A Must For Functional Verification


As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

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