Creating Better Models For Software And Hardware Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

A Different View On Debugging


The classic approach to improve an engineering task that is becoming too complex due to its size and detail is to raise the abstraction of design representation. In this way we plan cities, build aircraft and plan 500M gate SoCs. For example, there is no way an ASIC design could go beyond a few thousand logic gates without shifting abstraction to the Register Transfer Level (RTL) and leveragin... » read more

Why Is PSS So Important?


Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save. » read more

Addressing Pain Points In Chip Design


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Does System Design Still Need Abstraction?


About 15 years ago, the assumption in the EDA industry was that system design would be inevitable. The transition from gate-level design to a new entry point at the register transfer level (RTL) seemed complete with logic synthesis becoming well-adopted. The next step seemed to be so obvious at the time: High-level synthesis (HLS) and transaction-based development beyond RTL—also taking into ... » read more

How To Optimize Verification


The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Building An Efficient Inferencing Engine In A Car


David Fritz, who heads corporate strategic alliances at Mentor, a Siemens Business, talks about how to speed up inferencing by taking the input from sensors and quickly classifying the output, but also doing that with low power. » read more

Chiplet Momentum Builds, Despite Tradeoffs


Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

Raising The Abstraction Level For Power


Power-aware design is still a relatively new concern for many semiconductor products, and since inception it has changed several times and in different ways. Initially people were concerned about peak power. Today, they care about peak, total energy, thermal and other effects. The industry has tried several abstractions ranging from system-level analysis, which promised to swamp implementati... » read more

Defining Verification


There was a time when the notion of rigorous verification was seen as being unnecessary and even wasteful. I can remember early in my career working on flight control computers. We did no functional verification and created no models. We prototyped it and ran some engineering tests through it, primarily to structurally verify the system. We did not test the functionality of the system – that ... » read more

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