4 Issues In Test


When most design engineers think about test, they envision a large piece of equipment in the fab they probably will never actually see or interact with. But as chips become more complex—driven by an explosion in both quantity and different types of data—test is emerging as one of the big challenges in design and manufacturing. There are four primary segments for test, each with its own s... » read more

Making Sure A Heterogeneous Design Will Work


An explosion of various types of processors and localized memories on a chip or in a package is making it much more difficult to verify and test these devices, and to sign off with confidence. In addition to timing and clock domain crossing issues, which are becoming much more difficult to deal with in complex chips, some of the new devices are including AI, machine learning or deep learning... » read more

System-Level Testing – The New Paradigm for Semiconductor Quality Control


Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing methodologies including SiP, SoC, 3D finFETs, heterogeneous compo... » read more

ATE Lab To Fab


Shu Li, business development manager at Advantest, zeroes in on the communication gap between engineers on the design side and the manufacturing/test side, why it exists, and what needs to be done to bridge that gap in order to speed up and improve test quality. https://youtu.be/Nd-5_twbJBw     See other tech talk videos here » read more

Speedier, More Accurate Testing of Automotive Sensors Is Here


The amount of electronic content in automobiles continues to grow at a brisk pace, and sensors represent a significant percentage of cars’ electronics. MarketsandMarkets estimates that the automotive sensors market alone will reach US$36.42 billion in value by 2023, at a compound annual growth rate (CAGR) of 6.7 percent between 2017 and 2023. Sensors in cars are used to monitor and control... » read more

Boosting Regression Throughput By Reusing Setup Phase Simulation


This paper discusses how to write a design so the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. It also discusses what type of designs are appropriate for this methodology and what a designer can do to make his/her design suitable for it. Also c... » read more

What is STS Software Bundle?


The STS Software Bundle provides all the software tools and hardware drivers you need to efficiently develop and deploy test programs, interactively debug, and maintain and calibrate the NI Semiconductor Test System (STS). NI will release new bundles regularly to incorporate new functionality and hardware drivers. The STS Software Bundle includes tools for interactive measurements and debugg... » read more

Why Test Costs Will Increase


The economics of test are under siege. Long seen as a necessary but rather mundane step in ensuring chip quality, or a way of testing circuitry from the inside while it is still in use, manufacturers and design teams have paid little attention to this part of the design-through-manufacturing flow. But problems have been building for some time in three separate areas, and they could have a b... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology


This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

So Many Waivers Hiding Issues


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

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