Can engineers trust AI to get everything right in semiconductor design and verification?
Key Takeaways:
Semiconductor Engineering sat down to discuss the pros and cons of using agentic AI in chip design and verification, with Cindy Cui, vice president of global customer success at ChipAgents; Wally Rhines, CEO of Silvaco; Shelly Henry, CEO of Moores Lab AI; Dave Kelf, CEO of Breker Verification Systems; Vince Wong, head of AI development at Verific; and Ann Wu, CEO of Silimate. This panel discussion was held in front of a live audience at the recent 2026 ESD Alliance Executive Outlook meeting.
L-R: Breker’s Kelf; Silvaco’s Rhines; Verific’s Wong; Moores Lab AI’s Henry; Silimate’s Wu; ChipAgents’ Cui. Photo Credit: Paul Cohen, SEMI ESDA
SE: The hot new topic in EDA is agentic AI. Where will it help with semiconductor design and verification, and where do you see the potential problems.
Cui: Agentic AI will reshape the entire design flow. It’s already happening now. We’re talking about a lot of use cases, from DV to RTL generation, UVM, formal, and moving forward, from frontend to backend. It’s already helping a lot of engineers to speed up their design cycle. So it’s happening and it’s mature now. As for future challenges, we’re dealing with thousands of users globally, and we see the real challenge is not only the technology itself. It’s the organizational transformation — how to educate the engineer to get used to the new solution and to build teamwork. There are still a lot of things to do in that area. I see the entire industry will have to work together to help us get ready for that.
Wu: The tagline for our company is the co-pilot for chip designers. Today, what we do is build AI models and tools and agent harnesses that chip designers use. It’s enabling a much more directed and massive search of the design space. In previous generations of chip design, it was constrained because of the manual and compute constrained nature of it. Now you can generate a ton more experiments. You can do a lot more trial and error. One of the challenges we see, in addition to organizational, is how do you determine the quality of what you’re experimenting with? And how do you do that really quickly and accurately?
Henry: I’m coming from a user perspective. We have all these amazing tools from Cadence, Synopsys, Siemens, and the rest, and the engineers still take two years to build a chip. Why does it take two years? What is actually going on in those two years? How can we use AI to compress that down to three months? There are a lot of things we can do. We can generate designs. We can generate verification collateral. We can do debug. At the end of the day, it comes down to, ‘What’s the proof?’ You generate RTL code. How do you know that’s correct? And you generate a spec, and you generate code for that. How do you correlate and make sure that what you generate is correct for everything, even when you’re doing a testbench? How do you know that the testbench is correct? When you’re closing coverage, how do you know that nothing is getting accidentally thrown into the exclusion list. There are intricate things we do as engineers on a day-to-day basis. How can we get that automated through AI so that eventually it becomes a compressed schedule? The whole idea is how to build chips faster using AI.
SE: How much of that is on the design side, and how much of that is the ability to get on a fab shuttle, particularly at advanced nodes with test chips? Part of this is due to the fact that you can’t get capacity because it’s absorbed by all the big guys who are building chips.
Henry: All these big companies are building chips on a massive scale — hyperscalers like Google, Microsoft, Meta, Intel, AMD. And the fabs are all set up to cater to these big companies. If you’re a small company or a startup trying to build a chip, you’d be lucky to get a shuttle on TSMC in the next six months. That’s how the ecosystem is built. But I believe that AI technology will democratize the whole space, and there will be more people able to build chips cheaper and faster. That will bring up an ecosystem of fabs on the production side, as well.
SE: Back to the original question of where AI will help and where will it create problems?
Wong: On the plus side, it’s going to be much more productive for everybody. On the minus side, it’s too much trust in AIs. The AIs aren’t ready for us to just hand off everything and let AI do its thing autonomously. That’s the goal, but unfortunately, that’s not the reality. At this point, a lot of the flow cannot be automatic. It needs to have fixed points where human interaction is part of the pipeline. I don’t think there’s much emphasis on that today, but it’s something that’s going to creep up on us, and it should be a part of every methodology.
Rhines: You’re talking about accelerating the design part. There’s another part, which is the process, and that has been overlooked in this whole thing. The complexity of processes, and the amount of time it takes to run a prototype wafer, have made the traditional methods of physical prototyping impractical. We have to be able to build surrogate models for unit processes — the ability to do process integration on a computer instead of in a laboratory. That’s an enormous opportunity, because people who pay $25 billion for a wafer fab really place a lot of value on a one-month earlier ramp-up. They have a lot of money, and they spend money, unlike the EDA budgets that are controlled by R&D budgets of our customers. So it’s an enormous opportunity if you have 40 years of simulation data that you can put together in those surrogate models.
SE: This is really divide-and-conquer of a much more complicated design, right? There are a lot more elements here, particularly with agentic AI. How do you put all that together?
Rhines: A lot of us in the EDA industry are going to end up selling or renting agents, or providing our databases to customers who don’t want to reveal their proprietary information. We can give them an agent to work with their proprietary information to calibrate our synthetic data and make it fit with predictive norms for a process or a process capability.
Kelf: Over the last 30 years, we’ve sat on stages like this and said, ‘Chip design is moving along so quickly. How do we keep up? Where do we get the resources? The world’s falling in. What are we going to do about it? What’s the next stage?’ And all of a sudden, we have it. There’s no question that AI is going to make a huge, dramatic difference to our business. The question is, ‘How do we get there?’ So on one hand, a number of us are building AI into our tools. We’re improving efficiency and making these incremental changes. On the other hand, it seems there’s an opportunity to just throw away everything we’re doing and make a completely new flow. That’s been done before in EDA, and it’s usually horribly unsuccessful for a bunch of good reasons. Nevertheless, maybe this time something like that could be done. The problem is that chip design is not a business like recommending you watch the next 10 videos, where if it misses one it’s not really a big deal. This is an exact science. You can’t have a 1% error when you’re building a chip. It’s got to be right on. So the problem we’ve got to solve is how to get around that. How do we make sure these AI devices are exacting?
SE: How do you measure success with agentic AI?
Rhines: These are quality-oriented much more than they are quantity-oriented. Certainly, we’ll do designs in much less time. We will catch a lot more bugs than we would normally catch, and we will remove an enormous amount of drudgery of documentation, and the initial RTL generation, and the creation of the testbench and running testbenches. Those are all things that will relieve people to pursue the more creative aspects. But the quality that you generate in the ultimate design — or at least the quality in the intermediate steps — is what differentiates agentic AI from doing it the old way.
SE: Is the measurement of success at time zero, or is it over time?
Cui: The metrics will be an evolving system. In the past, AI could help one engineer to speed up. But with agentic AI, it can help the entire engineering organization speed up with trust. I call this a trusted acceleration. But moving forward, talking about T-0 and over time, this will eventually become a self-evolving engineering system. We really can build a system that can learn from all the previous experience, keep collecting feedback, and keep evolving from there. That’s the future AI solution for the industry.
Wu: It is going to be evolving, especially as the capabilities of systems that we’re designing evolve. There are outcomes and metrics that need to be anchored, and ultimately it’s outcome-based. From the software industry perspective, which is a leading indicator for us, and then even for our industry, there was this period where it was like, ‘How do we use AI? How do we ramp up AI usage to 100%?’ And now it’s, ‘The token budgets are out the window. Where’s the ROI? Where’s the efficiency?’ In my opinion, it’s not so much about evolving or specific metrics, but how can we do things that were previously not possible before agentic AI. That’s the litmus test for me and for the customers we work with. You can have speed-ups of 2X to 5X. You can automate certain processes that theoretically you can throw headcount at. We can talk about the talent gap as an issue, but the real issue is how do you compress timelines from 12 to 18 months down to 6 or 9 months. The answer to that is going to be new, hyper-efficient processes, and that’s going to come from the entire stack. Given this massive space that agents are set up to explore and propose ideas, how do you ascertain quality in a very short amount of time such that you can do this exploration, validation, and convergence in a fraction of the time.
Henry: This reminds me of a story a long time back. There was this math genius. He was on stage, and people in the audience were giving him three-digit numbers to multiply, like 342 times 287. The guy was giving the answer, and they were looking at the calculator and saying, ‘Oh, that’s correct.’ It was going well. And then there was this one guy in the audience who was drunk, and he got up and said, ‘Hey, I can do the same thing.’ Then someone from the audience gave him two numbers, 137 times 784. He immediately answered 7,432. They said, ‘That’s wrong.’ He said, ‘Hey, but I was fast.’ You can get a lot of things very fast, but how do you trust that? Can we build a chip out of it or not? We have the same problem today. We have different kinds of engineers. Some of them are really good, some not so great. How do we trust the output from these different engineers? That is still a problem. The way we try to solve that is we have different kinds of checkpoints and proof points and checklists. That is very ad hoc. It depends on the company you’re working at and the methodology they’re using. It would help if there is a consensus in the community about these qualities — like some benchmarks or proof points and things like that, which all these agents can strive toward — so that we have a consistent way of saying, ‘Okay, what is coming out is correct or benchmarked to a quality level.’
Kelf: I was going to mention benchmarks. We’re cooperating on this, trying to figure out a bigger flow and how we can work on this. One of the first things we came up with is, ‘Okay, if we’re going to cooperate, what kind of benchmark can we put in place to see how we’re actually going to improve things by working together. This is going to be a pie-growing exercise, where if we cooperate and work together to build in these different pieces, we can really make a big difference for the industry. If we all compete with each other, then it probably will all fall apart. Putting in place some metrics, some understanding of flows and what we achieve, and then seeing where we all fit into that, is a really critical part of it. If we can add to that and grow upon that, we stand a much bigger chance of making this really successful.
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