Benefits increase with package size, but not all the kinks have been worked out.
As a package substrate, the benefits of glass are substantial. It’s extremely flat with lower thermal expansion than organic substrates, which simplifies lithography.
And that’s just for starters. Warpage, a growing problem for multichip packages, is greatly reduced. Chips can be hybrid bonded to redistribution layer pads on glass. And relative to organic-core substrates, glass provides very low transmission loss for high-frequency and high-speed devices.
If that isn’t enough, silicon interposers and organic-core substrates are running out of steam. Glass is much cheaper than silicon interposers, and it has 50% less warpage and 35% better positional accuracy. That makes it easier to deliver redistribution layers (RDLs) with <2µm lines and spaces, which organic core substrates struggle to achieve. Additionally, the transparency of glass at communication wavelengths enables the embedding of waveguides into stacked glass structures for 6G applications. And ultrathin (<100µm) glass is readily fabricated in larger sizes of 700 x 700mm.
Glass — typically a borosilicate or quartz glass — is also flexible in its uses. It can be used as a carrier, a core substrate into which components are embedded, a 3D stacking material, or a hermetically sealed cavity for sensors and MEMS. Glass is a better conductor than organics, so it transfers heat away from active devices more effectively. Its coefficient of thermal expansion (CTE) can be tailored from 3 to 10 ppm/°C, making it more compatible with silicon on the low end, or PCBs on the high end.
Glass also shines in high-frequency applications. With a dielectric constant much lower than silicon’s (2.8 vs. 12) and low tangent loss, transmission losses are orders of magnitude lower than with silicon, greatly improving signal integrity.
For many years, glass has been gaining industry attention as the next-generation packaging substrate material due to its myriad benefits. A key feature is its ability to enable high interconnect density and RDL features below 2µm. “Punctuated by the surge in AI computing over the last two years, the need for condensing the wiring density to improve communication speeds within SiPs has become the focal point of IC-packaging R&D,” said Frank Wei, technology manager at Disco Hi-Tec America.
It’s not all perfect, though. Glass dicing (singulation) is difficult to perform without microcracking, and the challenge of repeatably fabricating thousands of fine-pitch through-glass vias (TGVs) at scale keeps glass from reaching its full potential. Intel invested heavily in glass substrate over the last 10 years and confirmed earlier this month that it is still proceeding with the glass program. Despite manufacturing barriers, the promise of improved HPC/AI chip quality is fueling rapid developments, as evidenced at the 2025 Electronic Components and Technology Conference (ECTC) and other recent conferences where researchers demonstrated progress in:
Stacking glass for high-frequency applications
Glass is ideal for 6G wireless communication networks, which must support >100 GHz data rates, due to its high frequency transmission with very low losses. Heterogeneous integration in stacked glass can integrate high-frequency front-end chips with low-loss interconnects in massive antenna arrays.
“By decomposing a transceiver module into individual functional chips, such as power amplifier and frequency converter, these chips can be embedded into stacked substrate cores and interconnected vertically,” said Xingchen Li, PhD candidate at the Georgia Institute of Technology. [1] Highlights of the process for stacking 2-inch (50 x 50mm) chips in a glass substrate include the integration of daisy chain structures, good alignment between glass layers (3µm), through-glass laser drilling, and copper fill.
The researchers chose an ABF (Ajinomoto Build-up Film, Dk = 3.3, Df = 0.0044) to function as both a low-k dielectric and an adhesive to glass, and RDL-based co-planar waveguides at two levels (see figure 1). Broadband electrical performance was achieved up to 220 GHz with 0.3 dB loss.
Fig. 1: Stacked glass architecture uses uncured ABF dielectric as adhesive, laser via drilling, and copper electroless seed/electroplated fill. Source: ECTC [1]
The 100 µm-thick glass panels were stacked using flip-chip bonding onto uncured ABF, which minimizes panel shift when heated. ABF encapsulates the chips, then another layer of uncured ABF (15µm) is laminated on the top glass and cured. Through-glass vias for both signal transmission and thermal improvement were formed using laser processing, followed by an adhesion promoter, electroless copper plating, and electrolytic plating to fill up V-shaped vias up to 130µm tall and 100 µm in pitch. The approach shows potential as a 3D stacking method for 6G applications.
Through-glass via (TGV) processes
Lasers play a pivotal role in the creation of TGVs. Richard Noack, strategic product manager at LPKF Laser & Electronics, recently detailed how laser-induced deep etching (LIDE) technology is being improved for production-level adoption. [2] LIDE starts with laser modification of borosilicate glass, which alters the structure and makes it susceptible to anisotropic etching.
The laser modification process disrupts the composition of the glass using a single laser pulse. “The initial modification is less than 1µm in width and can be described as a ‘chain of blisters,'” Noack said. “The etch rate along this gentle modification is 100 times higher compared to the rest of the material.”
Next, wet etching in hydrofluoric acid (HF) creates the desired shape (see figure 2). LIDE has demonstrated the ability to etch through-glass vias as small as 3µm and separated by a 5µm space.
To facilitate wet panel processing, Yield Engineering Systems (YES) developed an automated multi-chamber bath, rinse, and drying tool for processing up to 12 glass panels, 510 x 515mm in size. Venugopal Govindarajulu, senior director at the company, presented wet etching methods for fabricating high-AR through-glass vias designed for use in high-volume manufacturing. [3]
The tool can etch 25-100µm TGVs at an etch rate up to 80µm/hr at 130°C using commercially available glass materials. The laser process can be adjusted to achieve the desired shape – cylindrical, hourglass, straight via, or cavity.
The YES team determined that the etch rate and TGV profile are functions of the HF bath chemistry, acid concentration, and etching temperature, which can be tuned to achieve a highly selective etch (etch rate modified region/etch rate unprocessed glass) of 5:1.
An hourglass-like shape is considered ideally suited to enable void-free fill using copper PVD. The aspect ratio (depth/diameter) achieved with the wet etching bath ranged from 4:1 to 20:1 (200µm thick glass). “In a high-volume manufacturing environment, the key considerations are optimal chemistry for higher etch rate, fluid dynamics optimized for uniform etching, and good temperature and flow control for achieving process capability,” said Govindarajulu.
Fig. 2: An hour-glass shaped profile is most compatible with copper PVD seed layer followed by electrolytic plating. Source: ECTC [3]
Even though LIDE is considered the leading process for through-glass vias, companies are exploring more environmentally friendly solutions that do not involve toxic HF. Toshi Otsu and colleagues at the University of Tokyo were able to produce 6µm wide, 25µm pitch holes in 100µm thick Asahi Glass ENA1 material. [4] The method uses a collimated beam of deep UV laser (257nm) with different pulse energies and numbers of shots. “The use of an ultra-short pulsed laser minimizes thermal effects on the surrounding material, allowing for precise and clean processing,” the authors said.
Fig. 3: Hole depth increases with pulse energy but reaches a limit. Source: ECTC [4]
SEM cross-sections show the high-aspect-ratio TGVs have larger diameter holes at the glass top versus the bottom. Depth could be maximized to 260µm, with an aspect ratio between 20:1 and 25:1. (see figure 3). Future work will investigate how hole diameter is affected by changing the laser’s numerical aperture.
R&D to yield ramping of glass-core substrates
Any time the industry considers new materials such as glass, simulation can provide insights into how materials interact with one another. It can also help in comparing processes, such as which adhesion promoter interfaces best with glass, or whether PVD copper or copper electroless deposition forms a better seed layer.
“When moving to a novel type of substrate, such as glass, atomistic modeling will be a crucial tool to predict the behavior of the interfaces that form when putting multiple thin films on glass substrates. This provides direction as to where to focus one’s efforts, and what to pay attention to in the processing, before you even begin manufacturing”, said Anders Blom, principal solutions engineer at Synopsys.
Because glass is an amorphous material, it must be modeled using tens of atoms, as opposed to a material like crystalline silicon that requires only 2 atoms to begin modeling. “Recent advancements in GPU acceleration and machine-learning algorithms now allow us to use a combination of fast force fields and accurate first-principles modeling to build and run realistic models of such complex systems,” Blom noted.
Another tool that helps advance R&D and yield ramping at the panel level, especially for AI processors with HBM, is predictive yield modeling. John Chang, application development manager at Onto Innovation, presented details of a predictive yield model at ECTC with a special focus on overlay defects. “These components are expensive,” he said. “Therefore, maximizing yield at every step and identifying defects early to minimize losses is critical.”
Although glass core substrates significantly reduce pattern distortion and warpage relative to organic-core substrates, their occurrence can still impact yield in fan-out panel-level processing (FOPLP). The Onto Innovation approach uses an offline metrology tool to measure die shift and distortions, then combines it with customized process parameters and machine learning algorithms to quickly reduce overlay defects on 510 x 515mm panels. [5] “By utilizing predictive analytics and machine learning models, yield prediction technology not only identifies potential in-line process defects, but also recommends actionable solutions to optimize production parameters at an early stage, enabling a faster ramp-up,” said Chang.
Panel-level overlay errors typically exhibit a non-linear pattern across the panel, and four different correction methods are possible — global, zone-based (e.g., 4/panel), die-based, and site-by-site correction. Die-based corrections produce the highest yield, but the correction time drags down throughput. Instead, for each panel, a site-based correction exposes multiple dies per exposure in regions with similar shift, thereby maintaining high yield with less compromise on throughput. Yet that optimization alone provides less-than-acceptable yield.
Fig. 4: Yield prediction workflow enables real-time monitoring and analysis of die shifts and pattern distortions that affect overlay yield. Source: ECTC [5]
To accelerate the overlay improvement process, the team established a method to simulate the final yield as a function of different process parameter conditions. “By leveraging this technology (full flow in figure 4), users can identify optimal parameters through simulation and validate the predictions by running qualification substrates,” said Chang.
In addition, charts and histograms facilitate early identification of overlay issues in a production FOPLP environment, which helps accelerate qualification and streamline process optimization. “With the expected significant growth in FOPLP over the coming years, we believe that yield prediction technology will provide a clear path toward achieving rapid production and high yields in FOPLP lithography,” said Chang.
Preventing SeWaRe
Glass is known for its fragility. Microcracking is a major concern during handling and other operations, especially dicing.
Failures on glass-core substrates upon dicing are called SeWaRe, after the Japanese expression for “splitting of the back.” A study by Frank Wei and Andrew Frederick at Disco explored the cause of substrate cracking from dicing using both bare borosilicate glass of different thicknesses (125, 200, and 500mm), and also with two types of laminated build-up layers on both sides of the glass to arrive at the best known method for minimizing damage. [6]
The Disco study showed that the two-blade dicing methods created more edge chipping but smoother edges than the laser-based singulation methods (laser stealth and laser-enhanced ablation filling). Singulated die sizes were 5 x 5mm and 15 x 15mm. Importantly, the laminated layers improved die strength, and the best die strength was achieved with a higher modulus dielectric.
Finite element modeling (FEM) indicated that edge chipping is initiated by the sharpest microscopic defects, where stress is most concentrated during dicing. The Disco group determined that when laminated layers extend to the edge of the singulated region, SeWarRe defects occur. They can be eliminated by partially removing the laminated layers at the singulation edge, referred to as a pull-back method.
Fig. 5: When a pull-back method was used on the polymer build-up layers (front and back), chipping during singulation was eliminated. Source: ECTC [6]
While the mainstream process for glass panel singulation takes place after build-up layers are laminated on both sides of the substrates, Shun Mitarai and colleagues at Sony Semiconductor Solutions pursued a novel approach of embedding diced substrates in organic resin to provide edge protection. [7] They compared the singulated glass core embedding process (SGEP) to the industry’s conventional process. “The conventional process (CP) for manufacturing glass core substrates, while maintaining large glass panels, is straightforward, but requires significant investment for double-sided interconnect formation and extensive equipment modifications to handle the glass without breakage.”
The conventional process begins with TGV etching and metallization, followed by core interconnect processes. Then, the build-up layers are laminated, followed by singulation. Finally, organic resin is coated on each of the substrate’s edges.
Instead, the SGEP dices the substrate after the core interconnect formation. This novel step involves embedding the glass core segments into a copper-clad laminate frame. Then the build-up layers are laminated, followed by cutting the resin frame.
Mitarai points out that this protection process for individual glass edges is complex. The double-sided build-up layers effectively balance CTE-induced warpage associated with single-sided processing. Instead, the singulated glass core embedding process enables single-sided processing and provides superior substrate protection. Next steps for this approach will involve improving the process’s compatibility with stringent design rules and further improving yield.
Hybrid bonding on glass core
The flatness and positional accuracy of glass create new integration and process possibilities. “Unlike organic core substrates, the glass core substrates are flat enough to perform copper-copper hybrid bonding,” said John Lau, senior special project assistant at Unimicron. [8] He noted that glass is not a replacement for organic-core substrates. Instead, it complements the existing materials because smaller RDL lines and spaces may be manufactured using silicon dioxide dielectric and dual damascene processing.
The Unimicron team demonstrated both flip-chip bonding of devices to organic-core and glass-core substrates. They found that the warpage of flip-chip bonded hybrid bonding on glass was slightly larger than that of flip-chip bonded microbumping, but both were in the acceptable range. They attributed the lower warpage with microbumps to their ability to act as shock absorbers. The authors recommend using higher CTE glass (10 ppm/°C) when bonding to PCBs having a CTE in the 18 ppm/°C realm.
Conclusion
Companies in the glass ecosystem are making significant advances in preparation for a continued increase in chip and substrate sizes in multi-chip advanced packages. Laser modification followed by HF etching is the leading method for forming through-glass vias of different shapes and sizes, but direct laser etching using an excimer laser is a more environmentally attractive option if the process achieves the via shape needed for subsequent copper fill.
Glass microchipping during singulation, known as SeWaRe, may be preventable if consistent polymer pull-back can be implemented before blade or laser dicing. It appears that a switch in dicing method can reduce but not eliminate microcracks.
References
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Thanks, Laura!
Great article showing the status and challlenges of glass substrates