Chiplet Fundamentals For Engineers: eBook


Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Glass Substrates Gain Momentum


As a package substrate, the benefits of glass are substantial. It's extremely flat with lower thermal expansion than organic substrates, which simplifies lithography. And that's just for starters. Warpage, a growing problem for multichip packages, is greatly reduced. Chips can be hybrid bonded to redistribution layer pads on glass. And relative to organic-core substrates, glass provides very... » read more

Comprehensive Process Control Solutions For Through-Glass Vias


At some point in our lives, we have dropped a drinking glass or knocked over a glass-blown knickknack, only to watch it hit the floor and shatter into pieces. We learn from any early age that glass is fragile. But if glass is so fragile, why are manufacturers adopting glass core substrates? Good question. And one that comes with a ready answer. Glass is able to meet the new, denser line-s... » read more

On-Die And In-Package Interconnects: eBook


We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

Big Changes Ahead For Interposers And Substrates


Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems. This shift is being driven by AI, high-performance computing (HPC), and next-generation communications, where the need for heterogeneous ... » read more

Innovations Driving The Advanced Packaging Roadmap: Part Two


As the advanced packaging world enters the AI era, manufacturers are exploring ways to extend the life cycle of organic substrates and successfully introduce glass substrates to high volume manufacturing. In last month’s blog, “Innovations Driving The Advanced Packaging Roadmap: Part One,” we discussed the challenges of organic and glass substrates as the industry marches toward sub-2µm ... » read more

Innovations Driving The Advanced Packaging Roadmap: Part One


Advanced IC substrates (AICS) have been marching toward the 2µm line/space (L/S) redistribution layer (RDL) technology node for some time (figure 1). However, many questions remain about the ability of organic substrates to meet the line/space requirements of the next generation of advanced packages (AP), those below 2µm L/S and perhaps to 1.5µm L/S. Simply put: are organic substrates up to ... » read more

Monolithic Vs. Heterogeneous Integration


Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

3.5D: The Great Compromise


The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Custom Substrates Save Assembly Time, Resources


Time-to-market (TTM) and performance are two of the most pressing issues in chip design and manufacturing. Designing devices for high-speed, high-performance applications requires immediate access to substrates so that product development can proceed quickly. Quick substrate access is also vital to validating intellectual property (IP) cores used in application-specific ICs (ASICs) – all of w... » read more

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