The Rise Of Panel-Level Packaging

An insatiable demand for logic to memory integration for AI and high-performance computing is driving progress toward very large-format packages, which are expected to approach 10 times the maximum reticle size in the next few years.

These assemblies are best developed using fan-out panel-level packaging, replacing today’s wafer carrier with a panel. Fan-out packaging enables substantially lower cost than silicon interposers, while accommodating extra large die sizes with high I/O counts. But several developments on the equipment side are needed to improve alignment between layers, improve flip-chip placement of dies/assemblies on substrates, and control warpage and die shift through material and process advances.

Panel-level packaging already has proven useful in reducing the cost to produce small devices, such as smart watches, power management ICs (PMICs), and IoT devices. STMicroelectronics replaced the leadframe in quad-flat no-leads (QFN) packages with fan-out redistribution layers. Instead, it used redistribution layers (RDLs) for connectivity, thereby increasing productivity and reducing production costs. Such devices require much less aggressive RDL lines/spaces, such as 10/10µm, compared to 2/2µm leading-edge redistribution layer features that are more typically associated with high-performance computing.

Chipmakers are coalescing around organic interposers wherever possible, but glass-core is also making serious inroads.

“We are facing maybe the second wave of panel-level packaging, driven by HPC and AI,” said Tanja Braun, department head and group manager of assembly and encapsulation technologies at Fraunhofer IZM. In the first wave, fan-in and fan-out PLP became the go-to solution for cost-sensitive applications in consumer, automotive, high-frequency, and power devices. The second wave will tackle the more complex challenge of processing leading-edge devices using panel-level fan-out.

“At the moment we see a lot of progress in organic interposer technology and glass core substrates, which in the end is an extension of organic interposers because we use a glass core with organic ABF layers, RDL layers on both sides,” Braun said.

Panels offer a higher carrier utilization ratio than wafer-level processes, enabling improved material efficiency and less waste. “For larger chip sizes and AI, we need more and more memory and more compute power integrated in a single interposer,” said Teck Lee, technical director of R&D at ASE. “That is the driving force for larger and larger interposer sizes.”

Fig. 1: As interposer size grows, panel-level packaging provides much better utilization of the carrier area while reducing waste. Source: ECTC [1]

Panels also will be used in the manufacturing of substrates for advanced packaging. “We understand TSMC will support the NVIDIA Rubin Ultra package interposer with a 9.5X reticle size using a panel carrier,” said Yik Yee Tan, senior technology and market analyst, Semiconductor Packaging at Yole Group. This means TSMC will switch from CoWoS (Chip on Wafer on Substrate) to CoPoS (Chip on Panel on Substrate), from round to square processing on a similar 300mm size. We believe TSMC learned its strategy on 310 x 310mm panels before considering larger panel sizes in the future.” TSMC also is working toward 515 x 510mm panels.

The promise of panel-level packaging is clear from the skyrocketing numbers. Yole estimates that the panel-level packaging market will quadruple from 2024 ($160 million, 80,000 panels/~330,000 equivalent 300mm wafers) to $650 million, while the volume nearly triples to approximately 220,000 panels in 2030. [2]

Fig. 2: Panel-level packaging market forecast in thousands of units by panel carrier type. Source: Yole Group

Panel size depends on app
Such promise is enticing new players from the display and PCB worlds, which partly accounts for the wide variety of panel sizes being used. Panel sizes range from 310 x 310mm to 700 x 700mm.

“The choice of PLP panel sizes depends on whether the supplier is an existing display manufacturer, IC substrate manufacturer or a foundry as they may utilize their existing panel systems, which are standardized for the display and IC substrate markets, for PLP,” said Monita Pau, advanced packaging strategic marketing at Onto Innovation. Panel-level packaging potentially can leverage process tools used by today’s IC substrate, display, and PCB manufacturers to shorten the development of panel processing tools.

“The variability in panel size can be attributed to the discrete nature with which a manufacturer balances required capacity, yield, and I/O density to deliver the functionality of the package,” said Al Gamble, vice president of product marketing strategy at Onto Innovation.

Substrate players favor the 515 x 510mm size. The 415 x 510mm size is used in medical and industrial displays. SpaceX is planning to target 700 x 700mm panels for its FOPLP line. Nepes uses 600 x 600mm. Amkor, meanwhile, is pursuing 650 x 650mm panels for its production lines, which accommodate 4 300 x 300mm panels per 650mm glass panel. [3]

ASE’s Tek recently discussed the process changes around the 310 x 310mm panel, and fabricated a 10-chip, 10-bridge die test vehicle that included tall copper pillars and 3 redistribution layers (see figure 3). “Based on our analysis, if you look at the different interposer sizes, the utilization is not very different between a 300mm wafer and 300mm panel. But above 3.5X reticle size, the utilization goes up significantly and there is substantially less wasted panel. Also, the quality of the interposer you are getting on a 300mm panel is better than that on a 300mm wafer for packages larger than 3.5X reticle size.”

Fig. 3: ASE’s fan-out chip on substrate module features tall copper pillars (10µm diameter, 120µm tall), tight die-die spacing, and clean underfill. Source: ECTC [1]

Lithography compensates for die shift
RDL line/space features are large by fab processing standards, but the patterning process is tricky due to die shift caused by molding and other thermal processes. Laser direct imaging with compensation algorithms, such as Deca’s Adaptive Patterning, can adjust for die shift in multiple directions. Lithography based on steppers can more easily adjust for die shift in one direction. Deca’s technology uses a high-speed optical scanner to map the position of embedded features. [4] The software then generates an optimal layout for every die on the panel to compensate for process misalignment versus the designed feature. Maskless lithography (laser direct imaging) then creates the feature in the appropriate photoresist.

“The main lithography exposure tools used in redistribution layers for fan-out are steppers and laser direct imaging (LDI) tools,” said Eoin O’Toole, R&D director at Amkor Technology Portugal. “Steppers for advanced packaging have software capable of some level of stepping adjustment to compensate for die shift. Of course, steppers have reticle size restrictions, so many development efforts use the slower, less cost-effective process of laser direct imaging.”

Steppers are the most efficient at compensating for die shift due to temperature effects where clear scaling exists,” said O’Toole. “LDI systems are relatively inexpensive. However, some of the more evolved systems with elaborate algorithms can be as expensive or more expensive than steppers. And LDI tools typically require extensive offline measurements to fully compensate for die shift.”

Others concur on LDI’s limitations. “Serial imaging via laser-based technology is generally used for larger RDLs,” said Onto Innovation’s Gamble. “But it falls short of delivering the throughput needed to support high-volume manufacturing of next-generation technologies, which require much finer RDL structures to support AI and advanced compute. Parallel imaging via low-NA stepper technology — compatible with field sizes up to 250 x 250mm, and delivering >30 PPH throughput — is needed to meet the on-product imaging requirements (such as overlay, CDU, and depth of focus). It’s critical for R&D, yield ramp, and volume production. In turn, this enables benchmark levels of total cost of ownership, which drive time-to-market and profitability leadership of advanced packaging lines.”

While laser-direct imaging works for larger RDLs, the throughput needed to pattern finer-resolution RDLs requires multiple lasers to mitigate the productivity penalty. That penalty becomes more acute when high-volume manufacturing levels of productivity are needed. Laser direct imaging platforms that utilize multiple lasers are susceptible to stitching off-sets, both between individual lasers within the array as the scan propagates in one axis (e.g. the y-axis), and across the entire array as it steps in the x-axis. These issues become significant as RDL L/S resolution continues to shrink, often resulting in poor package-to-package and panel-to-panel repeatability and overlay performance.

Chip first versus RDL first versus mold first
Several process flows are being implemented in fan-out packaging (see figure 4).

Fig. 4: Different process flows for fan-out packaging. Source: Fraunhofer IZM

The chip-first (RDL last) approach is the most mature, but it has more serious yield ramifications than chip last. “The chip-first process benefits from being well established, which can lead to potentially lower manufacturing costs,” said Onto Innovations’ Pau. “However, it comes with notable challenges. One major drawback is the risk of die shift and warpage during processing, which complicates the scaling of the redistribution layer.”

Additionally, poor RDL yield can result in the loss of known good dies (KGDs), negatively impacting overall efficiency and cost-effectiveness. “On the other hand, in the chip-last approach, the RDL is tested before the KGD is attached, allowing for early detection of defects and improved yield,” Pau said. “Moreover, this method supports finer-pitch RDL scaling, as it avoids the additional warpage typically introduced by the molding compound. Despite these benefits, the chip-last method can be more expensive and demands extremely precise die placement onto the RDL formed on the carrier, which adds complexity to the process.”

Others agree. “If you look at the mold-first face-down approach, I like that quite a lot because it’s very easy to integrate different components, even from different suppliers with different pad metallization and so on,” said Fraunhofer’s Braun. “You have a carrier with a release tape and you place the chips face down on that tape. You do over molding in a large wafer or panel format, followed by a temperature step for carrier release. Then you build up the redistribution layer. In this process there is no interposer involved, or you could say the RDL is the interposer. RDL first is like an advanced flip chip on flex process, because you build up the RDL on the carrier, you do flip chip assembly on top of it, over molding, under filling, and then debonding from the carrier. And usually, you need silicon thinning and etching process steps and C4 bumping at the end.”

Wrestling with warpage
Substrate warpage is a critical issue for fan-out wafer level processes, which is only exacerbated at the larger panel level. Warpage is induced as assemblies containing materials with a variety of thermal expansion coefficients (CTEs) undergo thermal processes and shrink when they cool.

“Warpage issues have their origin mainly in the CTE difference between silicon (2.6ppm/°C) and the mold compound (7ppm/°C),” said Amkor’s O’Toole. The molding process is typically performed between 120°C to 150°C. As the substrate cools, CTE mismatch induces warpage in the reconstituted panel. “With a similar configuration, FOPLP will have a significantly higher warpage than a FOWLP as the CTE induced warpage scales with increasing dimensions. This warpage can be minimized by adjusting the silicon to mold proportions and overall thickness, if permitted.”

Other ways of containing warpage involve process control. “The quality of the C4 bump process is related to panel warpage after carrier debonding,” said ASE’s Lee. “A key factor is preventing handling issues during the C4 process.”

Carrier warpage has become so important that new materials are being developed to ease warpage potential. “Warpage management has become an essential requirement for yield manufacturing improvement in advanced packaging,” said Guillermo Zapico, principal engineer at TSMC. [5] His group tested a non-photosensitive polyimide from Hitachi Dupont Microsystems with comparable CTE to existing polyimide dielectrics, yet substantially lower cure temperature. They found the new material could meet the CD target for etched vias while reducing warpage by 79% on a silicon substrate, or 95% on a ceramic substrate.

Conclusion
Panel-level manufacturing is delivering economies of scale in the assembly of many non-leading-edge devices, but the greatest cost savings will come from delivering fan-out panel-level processes for AI/HPC devices by replacing silicon interposers with organic interposers. To make that happen, the FOPLP processes must meet the yields of current fanout wafer level packaging processes.

Today, both laser direct imaging and steppers are being used, but steppers are preferred for RDL patterning from a productivity standpoint. Likewise, thermocompression bonding is often used because it is more forgiving of warpage issues, while mass reflow is clearly favored for its productivity.

As new materials for interlayer dielectric, and molding materials with closer expansion coefficients to that of silicon, are brought into production, manufacturers will get a better handle on die shift and warpage. System-level optimization will be the focus for all of these complex AI/HPC packages.

References
1. T. C. Lee et al., “Advanced Packaging from FOWLP to FOPLP Development of FanOut Chip Last in 300 Mm Panel,” 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, TX, USA, 2025, pp. 537-541, doi: 10.1109/ECTC51687.2025.00095.
2. G. Pereira, “Is Panel-level Packaging Finally Emerging?” Yole Group, March 2025, https://www.yolegroup.com/strategy-insights/is-panel-level-packaging-plp-finally-emerging/
3. https://semiengineering.com/a-hybrid-plp-technology-based-on-a-650-mm-x-650-mm-platform/
4. G. F. Zapico et al., “Carrier Warpage Improvement Using Nonphotosensitive Dielectric Material for High I/O Density Organic RDL Application in Future Advanced Packaging,” 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, TX, USA, 2025, pp. 505-509, doi: 10.1109/ECTC51687.2025.00089.
5. C. Bishop et al., “M-Series Fan-Out Interposer Technology (MFIT) – Scaling Up for HPC & AI,” 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, TX, USA, 2025, pp. 515-521, doi: 10.1109/ECTC51687.2025.00091.

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