tag: CTE

Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics
By Laura Peters - 21 May, 2026 - Comments: 0

Key Takeaways: Tin-bismuth-based solders enable reduced warpage and compatibility with silicon photonics and other temperature-sensitive components. A novel soldering process using white light could help prevent cracks in flip-chip BGA package solder balls, while reducing the carbon footprint. Hypoeutectic Sn-Bi based solders prove especially promising as an SAC305 replacement. ... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Beating The Heat In 3D Packages
By Laura Peters - 25 Mar, 2026 - Comments: 0

Key Takeaways: Thermal management is a central design constraint, requiring early, thorough planning. Accurate thermal simulation requires AI-driven adaptive meshing and real-world validation. Innovative STCO strategies can drastically reduce GPU peak temperature. As HPC and AI accelerators push power densities to 1kW and beyond, the heat generated by rapidly switching tran... » read more

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

The Rise Of Panel-Level Packaging
By Laura Peters - 24 Jul, 2025 - Comments: 0

An insatiable demand for logic to memory integration for AI and high-performance computing is driving progress toward very large-format packages, which are expected to approach 10 times the maximum reticle size in the next few years. These assemblies are best developed using fan-out panel-level packaging, replacing today’s wafer carrier with a panel. Fan-out packaging enables substantially... » read more

Advanced Packaging Depends On Materials And Co-Design
By Katherine Derbyshire - 22 May, 2025 - Comments: 0

Multi-die assemblies offer significant opportunities to boost performance and reduce power, but these complex packages also introduce a number of new challenges, including die-to-RDL misalignment, evolving warpage profiles, and CTE mismatch. Heterogeneous integration — an umbrella term that covers many different applications and packaging requirements — holds the potential to combine com... » read more

Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Fine-Line RDL Structure Analysis of Fan-Out Chip-on-Substrate Platform
By ASE - 17 Apr, 2025 - Comments: 0

Abstract: "The demand for high bandwidth memory (HBM) has driven the need for advanced packaging solutions, particularly those involving fan-out layers to interconnect wafers within packages. To meet the high-bandwidth requirements of the Fan-Out Chip-on-Substrate (FOCoS) technology platform, additional layers are required. However, as the number of fanout layers increases, significant chall... » read more

Benefits And Challenges In Multi-Die Assemblies
By Ed Sperling And Laura Peters - 02 Apr, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of t... » read more

The Rise Of Thin Wafer Processing
By Laura Peters - 20 Mar, 2025 - Comments: 0

The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the amount of energy needed to drive them. Markets calling for ultrathin wafers are growing. The combined thickness of an HBM module with 12 DRAM dies and a base logic chip is still less than that of a ... » read more

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