Author's Latest Posts


Automated 310mm Panel-Level Packaging to Accelerate AI Innovation: Tech Brief


This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency. The larger panel format supports higher throughput, reduced cycle time, and lower cost per package, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC applic... » read more

Fine-Line RDL Structure Analysis of Fan-Out Chip-on-Substrate Platform


Abstract: "The demand for high bandwidth memory (HBM) has driven the need for advanced packaging solutions, particularly those involving fan-out layers to interconnect wafers within packages. To meet the high-bandwidth requirements of the Fan-Out Chip-on-Substrate (FOCoS) technology platform, additional layers are required. However, as the number of fanout layers increases, significant chall... » read more

Next Generation Chip Embedding Technology For High Efficiency Power Modules and Power SiPs


Cost, performance, and package size are some of the key drivers required in the next generation of package interconnect and package structure evolution. Embedding active die into substrates was mainly driven by package miniaturization for communication handheld devices. However, in the case of power modules, miniaturization is not the only driver that enhances the need for embedded die substrat... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last


The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

New Developments Of Copper Plating Technology For Embedded Power Chip Packages Challenges


Copper plating has been extensively employed in the fabrication of embedded packaging to reach high-density, high-speed, high performance electronic products. With through holes (TH) as well as blind via aspect ratios increase, development of a reliable plating technology is very important. When the depth of through hole was over 200µm, it is difficult to fill without void by using direct curr... » read more