Wirebonding Is Here To Stay

Few technologies in semiconductor manufacturing have stood the test of time as steadfastly as wirebonding. This process, which involves electrically connecting semiconductor devices to their packages, has been a cornerstone of the electronics industry since the beginning of the electronics industry. Like everything else in the semiconductor market, wirebonding technologies have changed over ... » read more

New Standards Push Co-Packaged Optics

Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature

A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

ILP-Based Router for Wire-Bonding FBGA Packaging Design

A new technical paper titled "ILP-Based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design" was written by researchers at National Taiwan University of Science and Technology. "In this paper, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-depende... » read more

Modeling and Thermal Analysis of 3DIC

A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

Cu/SiO₂ Hybrid Bond Interconnects

Technical paper titled "Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests" from researchers at TU Dresden and others. Abstract: "The focus of this study is a detailed characterization of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch... » read more

X-ray Imaging of Silicon Die Within Fully Packaged Semiconductor Devices

Abstract: "X-ray diffraction imaging (XRDI) (topography) measurements of silicon die warpage within fully packaged commercial quad-flat no-lead devices are described. Using synchrotron radiation, it has been shown that the tilt of the lattice planes in the Analog Devices AD9253 die initially falls, but after 100 °C, it rises again. The twist across the die wafer falls linearly with an incre... » read more

Expanding Advanced Packaging Production In The U.S.

The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow. The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North A... » read more

Research on the Humidity Resistance Reliability of Different Packaging Structures

Abstract "Packaging process is an indispensable part in the process of electronic components manufacturing, and its packaging quality directly affects the nominal power, reliability and other functions of the product in the subsequent application process. Through the research on the humidity resistance reliability of different packaging structures, C-Mount packaging structure, TO packaging str... » read more

Research on Wire Sweep of Integrated Circuit Packaging Based on Three-dimensional Flow Simulation

Abstract: "Semiconductor manufacturing technology is becoming more and more rapidly. In the process of Integrated Circuit (IC) encapsulation, when wires contact each other, it will cause short circuit. Wire sweep has become the main factor affecting the reliability of the product. Therefore, it is a great challenge to master wire sweep in IC packaging process. This paper takes Low Profile Fi... » read more

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