tag: Onto Innovation

Progress In Wafer And Package Level Defect Inspection
By Anne Meixner - 09 Apr, 2024 - Comments: 0

The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

New Strategies For Interpreting Data Variability
By Gregory Haley - 09 Apr, 2024 - Comments: 0

Every measurement counts at the nanoscopic scale of modern semiconductor processes, but with each new process node the number of measurements and the need for accuracy escalate dramatically. Petabytes of new data are being generated and used in every aspect of the manufacturing process for informed decision-making, process optimization, and the continuous pursuit of quality and yield. Most f... » read more

Using Automatic Defect Classification To Reduce The Escape Rate Of Defects
By Bryce Chi - 09 Apr, 2024 - Comments: 0

Automated optical inspection (AOI) is a cornerstone in semiconductor manufacturing, assembly and testing facilities, and as such, it plays a crucial role in yield management and process control. Traditionally, AOI generates millions of defect images, all of which are manually reviewed by operators. This process is not only time-consuming but error prone due to human involvement and fatigue, whi... » read more

Non-Destructive Metrology Techniques For Measuring Hole Profile In DRAM Storage Node
By Onto Innovation - 09 Apr, 2024 - Comments: 0

DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot... » read more

Digital Twins Target IC Tool And Fab Efficiency
By Laura Peters - 21 Mar, 2024 - Comments: 0

Digital twins have emerged as the hot "new" semiconductor manufacturing technology, enabling fabs to create a virtual representation of a physical system on which to experiment and optimize what's going on inside the real fab. While digital twin technology has been in use for some time in other industries, its use has been limited in semiconductor manufacturing. What's changing is the breadt... » read more

Using Picosecond Ultrasonics To Measure Trench Structures In SiC Power Devices
By Nick Keller - 12 Mar, 2024 - Comments: 0

The road to the future is not always a smooth, trouble-free drive. Along the way, there may be unforeseen detours, potholes and accidents, each one capable of setting progress back. But for those behind the wheel, those obstacles are just a part of the journey. Such is the case for the automotive industry as it continues to steer away from gas-powered vehicles and turn toward hybrid and elec... » read more

AI/ML Challenges In Test and Metrology
By Gregory Haley - 12 Mar, 2024 - Comments: 0

The integration of artificial intelligence and machine learning (AI/ML) into semiconductor test and metrology is redefining the landscape for chip fabrication, which will be essential at advanced nodes and in increasingly dense advanced packages. Fabs today are inundated by vast amounts of data collected across multiple manufacturing processes, and AI/ML solutions are viewed as essential for... » read more

Why Chiplets Are So Critical In Automotive
By John Koon - 20 Feb, 2024 - Comments: 1

Chiplets are gaining renewed attention in the automotive market, where increasing electrification and intense competition are forcing companies to accelerate their design and production schedules. Electrification has lit a fire under some of the biggest and best-known carmakers, which are struggling to remain competitive in the face of very short market windows and constantly changing requir... » read more

Blog Review: Feb. 14
By Liz Allan - 14 Feb, 2024 - Comments: 0

Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Using OCD To Measure Trench Structures In SiC Power Devices
By Nick Keller - 08 Feb, 2024 - Comments: 0

You don’t have to be a dedicated follower of the transportation industry to know it is in the early stages of a significant transition, away from the rumbling internal combustion engine to the quiet days of electric vehicles. The signs of this transition are right there on the streets in the form of electric-powered buses, bikes and cars. The road to our electric future is before us, but we w... » read more

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