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Scaling Bump Pitches In Advanced Packaging


Interconnects for advanced packaging are at a crossroads as an assortment of new package types are pushing further into the mainstream, with some vendors opting to extend the traditional bump approaches while others roll out new ones to replace them. The goal in all cases is to ensure signal integrity between components in IC packages as the volume of data being processed increases. But as d... » read more

High Thermal Die-Attach Paste Development For Analog Devices


Authors: Kiichiro Higaki, Toru Takahashi, Akinori Ono from Assembly Engineering Department Amkor Technology Japan, Inc. Keiichi Kusaka, Takayuki Nishi, Takeshi Mori from Information & Telecommunication Materials Research Laboratory, Sumitomo Bakelite Company, Limited Daisuke Koike, Masahiko Hori from Package Solution Technology Development Department, Electronic Devices & Storage Res... » read more

System-In-Package Thrives In The Shadows


IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

Qualifying The ExposedPad TQFP For AEC-Q006 Grade 0


Semiconductor packages used in various vehicle applications require high reliability. As technological innovations in the automotive market increase, the demand for highly reliable packaging is increasing for applications in autonomous driving, human interfaces, electric vehicles (EVs), hybrid electric vehicles (HEVs) and more. Package reliability is essential because automotive packages must p... » read more

Challenges With Chiplets And Packaging


Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Intel plans to establish foundry capacity at its fab in Ireland. The company has also launched the so-called Intel Foundry Services Accelerator to help automotive chip designers transition from mature to advanced nodes. The company is setting up a new design team and offering both custom and industry-standard intellectual property (IP) to support the needs of automotive custom... » read more

Manufacturing Bits: Aug. 24


Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

Current And Future Packaging Trends


Semiconductor Engineering sat down to discuss IC packaging technology trends and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Thomas Uhrmann, directo... » read more

Empowering RF Front End Cellular Innovations With DSMBGA


With the introduction of 5G, cellular frequency bands have increased considerably, requiring innovative solutions for the packaging of RF front-end modules for smartphones and other 5G-enabled devices. Double-sided, molded ball grid array (DSMBGA) is a prime example of such solutions. “With our DSMBGA platform, we’ve established a preferred advanced packaging solution for this domain,”... » read more

Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS


Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fanou... » read more

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