Chip Industry Week In Review

By The SE Staff - 19 Jun, 2026 - Comments: 0

Dealmaking Amkor inked a 10-year agreement with TSMC to provide advanced packaging and test services in Arizona, tying TSMC’s U.S. fab expansion to domestic OSAT capacity. Trump said in a post that Apple will partner with Intel on chip design and production in the U.S., marking a second reported win for the chipmaker this month. Intel Foundry will also reportedly manufacture 3 million... » read more

Scaling ADAS To 10+ Cameras

By WonBae Bang - 18 Jun, 2026 - Comments: 0

By WonBae Bang, KiDong Sim, Weilung Lu, and Adrian Arcedera Introduction Advanced Driver Assistance Systems (ADAS) are increasingly adopted by automotive manufacturers to enhance driving safety. These systems help drivers in the driving process, thereby increasing car and road safety. ADAS technologies include features such as adaptive cruise control, lane departure warning and automatic emer... » read more

Making On-Chip Photonics Manufacturable

By Gregory Haley - 18 Jun, 2026 - Comments: 0

Key Takeaways: System-level energy and bandwidth pressures are pulling optics into the package faster than the manufacturing flow can mature. Photonics combines front-end fabrication, materials, thermal, cleanliness, and test into one problem that can’t be solved domain by domain. Test is moving upstream because discovering an optical failure after final assembly forfeits every goo... » read more

Co-Packaged Optics Testing Faces Steep Data Center Ramp

By Anne Meixner - 09 Jun, 2026 - Comments: 0

Key Takeaways: Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, and interference. Advanced data management practices will help speed yield learning. Integrating photonic and electrical ICs into co-packaged optics (CPO) requires... » read more

AI Accelerator Testing Depends On DFT Innovations

By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield

By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Chip Industry Week in Review

By The SE Staff - 01 May, 2026 - Comments: 0

Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

When Semiconductor Materials Misbehave

By Gregory Haley - 27 Apr, 2026 - Comments: 0

Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

TSV Complexity Leads To Manufacturing Bottleneck

By Laura Peters - 22 Apr, 2026 - Comments: 1

Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality

By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

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